CoreLink SSE-200 subsystem

The ARM® CoreLink SSE-200 subsystem is the fastest way to get your next project to tape-out and to create successful secure IoT chips. It integrates the core components of your system in a validated foundation that you can trust.

The flexible architecture for your future secure IoT designs


Building security into an embedded system and integrating all the necessary components take a significant amount of time and effort. The CoreLink SSE-200 subsystem aims to make this difficult process easier, by integrating and validating ARM IP in one system. The CoreLink SSE-200 subsystem is based on a two-core structure, and integrates features you would expect to find in best-in-class IoT chips. The CoreLink SSE-200 subsystem integrates the following ARM IP:

  • ARM Cortex®-M33 processor
  • ARM CoreLink SIE-200
  • Instruction caches with ARM TrustZone® support
  • Power infrastructure components
  • CoreSight SoC
  • ARM TrustZone CryptoCell (option)
  • ARM Cordio® Radio (option)

CoreLink SSE-200 key features

Two cores

Having two cores in a system can often be more efficient than running a single core. When you combine two cores, you can have different operating points for each processor. This means that you can dynamically switch one of them to adapt to different processing and power-consumption needs.

Examples of usage cases:

  • Battery-powered IoT sensor – In this example, the system is in hibernation most of the time. The first core is used to regularly manage the device and acquire sensor data. The second core could be switched on only when a peak of activity is necessary (for example: to perform data reduction, sensor fusion or to manage complex communication processing like LTE Cat-NB1)
  • Product connected to power outlet – In this case, the first core might be used to manage the system in the background, while the second would be used for user interface, machine learning tasks or motor control, for example.

The benefits of a two-core architecture include:

  • Low-power – Having two cores allows you to reduce power consumption in a system by powering only the necessary processing at any time, rather than using a more powerful core that would consume energy all the time.
  • More powerful – At implementation time, it is possible to select different configurations for each processor (for example: maximum frequency, DSP/Floating-point capability, coprocessor), each of them can run in parallel and get the greatest performance out of the system.
  • Flexibility – The system adapts dynamically to the needs of the device.


The CoreLink SSE-200 subsystem has been designed to adapt to different use cases: options, customizable logic blocks and many configuration points are provided to tune it to your particular needs.

For example, it is possible to select a minimal configuration with a single core, no radio and no security acceleration, or to pick all the options and use all possible extension capabilities of the Cortex-M33 processor, to enable a high performance system.

Another important customization area is the power management of the system. Designers have the opportunity to add their own logic to manage automatic clock and power gating using the provided infrastructure. This allows designers to take into account all the characteristics of the SoC and implement an efficient chip-level power-saving scheme.

Power efficiency

The CoreLink SSE-200 subsystem contains a very advanced power and clock control infrastructure, using the latest AMBA Low Power Interface Specification for communication between the different domains.

Automatic hierarchical clock gating is already implemented so that designers have it readily built for them. Power gating is also integrated, to allow an optimization of the power consumption of the device in very constrained battery-powered applications.

Designers using the CoreLink SSE-200 subsystem just have to add their own gating rules in the customizable power control blocks, to adjust to the exact parameters of the complete system and tune the performance to the selected blocks involved in clock and power management: oscillators, PLL, PMU etc.

The CoreLink SSE-200 subsystem also contains an “always-on” domain that keeps synchronization and controls system wake-up. Running from a low frequency clock (e.g. 32.768 kHz), it ensures that the rest of the system can safely enter hibernation mode and be switched off.

In cases where a fast wake-up is necessary, memory retention can be selected to save the current state while the system is sleeping.

All these leading-edge power-saving features usually take a lot of time and effort to implement and verify. With the CoreLink SSE-200 subsystem, it is built and verified for you!

Secure debug

Securing the debug port is important to avoid access to code and keys in a system. The CoreLink SSE-200 subsystem implements a certificate-based secure debug access together with TrustZone CryptoCell.


Having instruction caches in the CoreLink SSE-200 allows you to increase the performance by making sure the processor is rarely waiting to access code. When used with embedded Flash, this caching system is also a great way to reduce the system power consumption, by significantly decreasing the number of power-consuming read accesses.

A specific power and clock island isolates the second processor, so that it can run at a higher frequency than the rest of the system (with a ratio of up to 32x). Since the second core has its own cache and tightly coupled memory, the efficiency and performance are maximized while the rest of the system remains in a lower power mode.