Virtual Debug Interface (VSTREAM)
Systems are getting more complex. More cores, more peripherals, GPU integration and a complex memory hierarchy. Tackling this complexity with system level validation from the early stages of product development helps your engineering team to avoid potential problems that might otherwise surface after tape-out. VSTREAM brings all the features of the powerful ARM DS-5 Debugger to your emulator or RTL simulator to make this process rapid.
Connect to the Leading Emulators and RTL Simulators
VSTREAM is a fast and flexible virtual debug interface that connects software debuggers to hardware assisted verification systems such as Cadence Palladium, Synopsys (formerly Eve) ZeBu and Mentor Veloce and RTL simulators like Cadence Incisive, Mentor ModelSim & Questa and Synopsys VCS.
All the Features of a Debug Adapter, Virtually
VSTREAM enables the stop-mode debug features usually available in professional debug adapters including stopping the processor, view and change the value of processor registers and system memory and single-step through code. However, this is not via a physical JTAG connection, but via SCE-MI2 or ZEMI-3 transactors directly into the SoC RTL. Not only is this virtual connection much faster, but it is also easier to start remotely, not requiring any modification to the emulator hardware set-up.
- Features & Specification
- Supports all ARM Cortex processors
- Supports Mentor® Veloce®, Synopsys® ZeBu® and Cadence® Palladium® series emulators
- Virtual solution: no hardware required
- Supports Cadence Incisive, Mentor ModelSim & Questa and Synopsys VCS RTL simulators
- Remote access over TCP/IP, remote target reset
- Code download speeds of over 200 KBps
- Code stepping at 1.5 steps/s
- On-chip trace buffer support
- Emulator workstation requires Red Hat Enterprise Linux 5
DS-5 and VSTREAM Integration
The ARM DS-5 suite is the ideal companion to VSTREAM. Used together they can help verify the correct implementation of the debug and trace fabric of the SoC, including any CoreSight components, by running high-level test patterns and connecting an actual debugger to the RTL simulator. The connection of the processor to the memory system and memory-mapped peripherals can be validated easily by opening memory views in the debugger. Instead of finding problems with a design's debug architecture after tape-out they can now be found in the RTL.
VSTREAM supports post-process PTM™ and ETM™ instruction trace after a simulation run in order to get a history of instructions executed by the processor in a non-intrusive way.
Read the VSTREAM product brochure.
Contact us for details.