The Foundation for Building Better Systems

Arm System IP enables system designers to configure and build performant, power efficient SoCs whilst further differentiating by combining Arm processors with their own IP elements via industry standard AMBA interfaces. Arm interconnects, debug and trace components and controllers are scalable across many different applications, from tiny IoT devices to large enterprise SoCs. 

Click on a block in the diagram below to find out more:

Cache coherent interconnect

Optimized for the highest efficiency coherent interconnect applications including big.LITTLE processing, configurable in area and power to be scalable across multiple applications.

CoreSight Debug & Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core. 

Memory Controllers

High bandwidth and low latency access to memory across LPDDR3/4 memory types for best-in-class performance and power efficiency. 

Network interconnect

Highly configurable low latency interconnects used for rest of SoC connectivity, as well as non-coherent traffic in single cluster systems.

Generic interrupt controller

An exclusive block of IP that performs critical tasks of interrupt management, prioritization and routing. GICs are primarily used for boosting processor efficiency and supporting interrupt virtualization.

Memory management unit

Responsible for all aspects of memory management, including caching and memory virtualization, it gives a common view of memory to all SoC components.

IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, configuration and integration to help designers build better SoCs.

TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.