Arm CoreLink Interconnect

Arm CoreLink Interconnect provides the components and the methodology for designers to build SoCs based on the latest Arm AMBA specifications, maximizing the efficiency of data movement and storage, delivering the performance needed at the lowest power and cost. There are three CoreLink Interconnect families, each optimized for their target applications. High performance SoCs with multiple processor clusters would include a Cache Coherent Interconnect, combined with CoreLink Network Interconnect to provide connectivity for the whole SoC.

Highest Performance Coherency


CMN-Chip Image


CoreLink Coherent Mesh Network

  • Designed for scaling to the highest performance infrastructure applications including networking and servers
  • Offering scalable system coherency in multi-core heterogeneous processor systems
  • Highly configurable and scalable CoreLink CMN-600
  • Previous generation: CoreLink CCN-512, CCN-508, CCN-504 and CCN-502
  • Find out more CMN
  • Find out more CCN

Highest Efficiency Coherency


CoreLink Cache Coherent Interconnects

CoreLink Cache Coherent Interconnect

  • Optimized for the highest efficiency coherent applications including mobile big.LITTLETM processing
  • Offering the smallest and lowest power multi-cluster interconnect
  • Family consists of: CoreLink CCI-550, CCI-500, CCI-400
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Network on Chip (NoC)


CoreLink Network Interconnect Family


CoreLink Network Interconnect

  • Fully configurable for SoC connectivity across all applications
  • Hierarchical, low latency and low power connectivity
  • Back plane for smaller, single processor designs
  • Companion interconnect for I/O coherency and rest of SoC connectivity with CoreLink CCI and CCN
  • Family consists of: CoreLink NIC-450, NIC-400 and NIC-301
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CoreLink Interconnect Family Comparison

 Product CoreLink CMN-600 and CoreLink CCN Family  CoreLink CCI Family CoreLink NIC Family
 Summary Scalable range of high performance, power efficient coherent interconnects targeting network infrastructure and servers Configurable interconnect for power and area sensitive applications including mobile big.LITTLE processing, set top box, digital TV, automotive and low cost network infrastructure Low latency interconnect for rest of SoC connectivity, or single cluster processing such as wearables or embedded
 Processors Up to 32 clusters (128 cores) Up to 6 clusters (24 cores) or CPU & GPU coherency Configurable, non-coherent
 AMBA Interface AMBA 5 CHI AMBA 4  ACE and AXI4 AMBA 4 AXI4, AXI3, AHB-Lite, APB
 Bus Width 128 or 256 bit transport  128 bit Configurable 32 to 256 bit
 Memory Channels 1-8 Channels up to x64 bit 1-6 Channels up to x32 bit Configurable
 I/O Interfaces Up to 96 AXI4 / ACE-Lite interfaces Up to 0-6 ACE-Lite Connects multiple devices to CCI and CCN

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