CoreLink CCI-400

The Arm CoreLink CCI-400 Cache Coherent Interconnect

Premium Mobile CCI400 System Diagram.

Getting Started

The Arm CoreLink CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs. It enables big.LITTLE processing and I/O coherency for devices such as the Mali-T600 series GPU, and I/O masters like modem and USB. First released in 2011, CoreLink CCI-400 has been widely licensed and is today shipping in many millions of production devices.

Specifications

 Features Details
 AMBA Specifications
AMBA 4 ACE and ACE-Lite
 ACE Slave interfaces 2 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 1-3 for IO coherent devices such as Mali processors, accelerators and IO
 Memory and System master interfaces

1-2 memory interfaces
1 system interface

 Coherency
Broadcast snoop protocol
 Memory map 40 bit Physical, configurable address map
44 bit DVM


  • TRM
  • CoreLink CCI-400 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-400 TRM
  • A guide on software optimization.
  • AMBA 4 ACE Specification

    CoreLink CCI-400 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.
  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.



    Learn more

Get support

Community Forums

Not answered When should APB slave Sample address/Data for read/write transaction from APB master? 0 votes 33 views 0 replies Started 6 days ago by arm_user Answer this
Not answered Timing simulation with ARM standard library 0 votes 38 views 0 replies Started 8 days ago by Yongchan Jeon Answer this
Not answered Can the ARM corrupt the timing on the AXI bus
  • SoC FPGA
  • Timing & Addressing
0 votes 62 views 0 replies Started 13 days ago by skbrown Answer this
Suggested answer Cycle Model Studio software
  • Cycle Model Studio
0 votes 198 views 1 replies Latest 19 days ago by Jason Andrews Answer this
Suggested answer why PSTRB signal in APB4 have four bits?
  • AMBA 4
0 votes 448 views 2 replies Latest 1 months ago by Colin Campbell Answer this
Not answered [ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface! 0 votes 188 views 0 replies Started 1 months ago by jaycekr Answer this
Not answered When should APB slave Sample address/Data for read/write transaction from APB master? Started 6 days ago by arm_user 0 replies 33 views
Not answered Timing simulation with ARM standard library Started 8 days ago by Yongchan Jeon 0 replies 38 views
Not answered Can the ARM corrupt the timing on the AXI bus Started 13 days ago by skbrown 0 replies 62 views
Suggested answer Cycle Model Studio software Latest 19 days ago by Jason Andrews 1 replies 198 views
Suggested answer why PSTRB signal in APB4 have four bits? Latest 1 months ago by Colin Campbell 2 replies 448 views
Not answered [ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface! Started 1 months ago by jaycekr 0 replies 188 views