About CoreLink CCl-400
The Arm CoreLink CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs. It enables big.LITTLE processing and I/O coherency for devices such as the Mali-T600 series GPU, and I/O masters like modem and USB. First released in 2011, CoreLink CCI-400 has been widely licensed and is today shipping in many millions of production devices.
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CoreLink CCI-400 highlights
| AMBA Specifications
||AMBA 4 ACE and ACE-Lite|
|ACE Slave interfaces||2 for fully coherent processors including Arm Cortex|
|ACE-Lite slave interfaces||1-3 for IO coherent devices such as Mali processors, accelerators and IO
|Memory and System master interfaces||
1-2 memory interfaces
||Broadcast snoop protocol
|Memory map||40 bit Physical, configurable address map
44 bit DVM
CoreLink CCI-400 key features
1st Generation Cache Coherent Interconnect
Mature and silicon proven, widely licensed and shipping in many millions of devices.
Supporting smaller 2 cluster and 1 or 2 memory interfaces, the CoreLink CCI-400 is the smallest cache coherent interconnect available from Arm.
CoreLink CCI-400 Technical Reference Manual
For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.CCI-400 TRM
AMBA 4 ACE Specification
CoreLink CCI-400 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency system designs.AMBA specs
Extended System Coherency
A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.
This paper focuses on the AMBA ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, Distributed Virtual Memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE software to run effectively, increasing system efficiency.
Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.
Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.
This white paper explains a new mechanism for reducing the congestion in systems via QoS Virtual Networks. QVN makes system latency and bandwidth deterministic and predictable; preventing blocking in the interconnect by ensuring that a transaction can be accepted before it’s initiated.