CoreLink CCI-500

The Arm CoreLink CCI-500 Cache Coherent Interconnect

Getting Started

The Arm CoreLink CCI-500 Cache Coherent Interconnect extends the performance and low power leadership of Arm mobile systems. It provides full cache coherency between big.LITTLE processor clusters and provides I/O coherency for other agents such as Mali GPU, network interfaces or accelerators. CoreLink CCI-500 offers a scalable and configurable interconnect which enables SoC designers to meet the performance goals with the smallest possible area and power.


Specifications

 Features Details
 AMBA AMBA 4 ACE and ACE-Lite
 ACE slave interfaces 1-4 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 0-6 for IO coherent devices such as Mali processors, accelerators and IO such as PCIe root complex
 Memory and System master interfaces 1-4 memory interfaces
1-2 system interfaces
 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

  • TRM
  • CoreLink CCI-500 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-500 TRM
  • A guide on software optimization.
  • AMBA 4 ACE Specification

    CoreLink CCI-500 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency designs.

    AMBA specs
  • A program that is running on a desktop.
  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more
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  • System Validation at Arm

     Enabling Partners to Build Better Systems

    Download
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  • Introduction to AMBA 4 ACE

    This paper focuses on the AMBA ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, Distributed Virtual Memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE software to run effectively, increasing system efficiency.

    Download
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  • Quality of Service (QoS) in Arm Systems: An Overview

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.

    Download
  • A program that is running on a desktop.
  • QoS for High-Performance and Power-Efficient HD Media... - Arm

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

    Download

Introduction Video

Learn more about CoreLink CCI-500 features, applications and benefits.

Watch video


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Answered How to analyze critical function(in kernel module) that caused CPU-bound task by streamline?
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0 votes 84 views 1 replies Latest 7 days ago by Jason Andrews Answer this
Answered Skip U-Boot and Jump to kernel from U-Boot SPL (Falcon Boot)
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Discussion Looking for activation code of DS-5 Community Edition
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Answered DS-5 debugger hover functionality not working
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Answered Recovering from a hard fault cortex M3
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Answered Code not working on LPC2148 board
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0 votes 6994 views 9 replies Latest 3 months ago by Israa Answer this
Answered How to analyze critical function(in kernel module) that caused CPU-bound task by streamline? Latest 7 days ago by Jason Andrews 1 replies 84 views
Answered Skip U-Boot and Jump to kernel from U-Boot SPL (Falcon Boot) Latest 13 days ago by Bharat@Embedded 4 replies 325 views
Discussion Looking for activation code of DS-5 Community Edition Latest 24 days ago by jackhab 17 replies 5071 views
Answered DS-5 debugger hover functionality not working Latest 2 months ago by josecm 2 replies 572 views
Answered Recovering from a hard fault cortex M3 Latest 2 months ago by adolgo1 2 replies 517 views
Answered Code not working on LPC2148 board Latest 3 months ago by Israa 9 replies 6994 views