CoreLink CCI-500

The ARM® CoreLink™ CCI-500 Cache Coherent Interconnect

About CoreLink CCI-500

The ARM CoreLink CCI-500 Cache Coherent Interconnect extends the performance and low power leadership of ARM mobile systems. It provides full cache coherency between big.LITTLE™ processor clusters and provides I/O coherency for other agents such as Mali™ GPU, network interfaces or accelerators. CoreLink CCI-500 offers a scalable and configurable interconnect which enables SoC designers to meet the performance goals with the smallest possible area and power.

Premium mobile system with CoreLink CCI-500

CoreLink CCI-500 Performance

CoreLink CCI-500 key features

Up to 2x Peak System Bandwidth

Premium mobile devices are driving higher resolution screens such as 4K Ultra-HD content, external displays, and console quality gaming content.

  • CoreLink CCI-500 offers up to 2x peak system bandwidth compared to CoreLink CCI-400
  • Supporting up to 4x channel memory systems (e.g. 4x LPDDR4) for tablet and clamshell
     

Processor Memory Performance

CoreLink CCI-500 can offer greater than a 35% processor memory performance increase compared to CoreLink CCI-400. This is enabled by an enhanced micro-architecture including snoop filter which offers reduced snoop latency. 

TrustZone Secure Media Path

End to end protection for Ultra-HD media content, between memory, Mali GPU, video processors and display.

Configurability and Scalability

Highly scalable interconnect allowing optimal area/performance trade-offs and suitability for a wide range of applications. Scalable from one to four coherent clusters. Full support for today’s two-cluster big.LITTLE technology. Optimised for mobile and extendable to other applications such as cost efficient infrastructure compute, digital TV and automotive infotainment.

Part of a complete system solution from ARM

CoreLink CCI-500 is part of a complete suite of system IP from ARM including CoreLink NIC-400 network interconnect for low power, low latency, end to end connectivity to the rest of the SoC, CoreLink MMU-500 System MMU for virtualization of memory and CoreLink GIC-500 for management of interrupts across multiple processor clusters.

CoreLink CCI-500 highlights

 Features Details
 AMBA AMBA 4 ACE and ACE-Lite
 ACE slave interfaces 1-4 for fully coherent processors including ARM Cortex
 ACE-Lite slave interfaces 0-6 for IO coherent devices such as Mali processors, accelerators and IO such as PCIe root complex
 Memory and System master interfaces

1-4 memory interfaces
1-2 system interfaces

 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

Introduction Video

Learn more about CoreLink CCI-500 features, applications and benefits.

Useful Documentation

  • TRM
  • CoreLink CCI-500 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-500 TRM
  • AMBA 4 ACE Specification

    CoreLink CCI-500 is built on the AMBA® AXI4 specification, targeting high bandwidth, high clock frequency designs.

    AMBA specs
  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more
  • System Validation at ARM

     Enabling Partners to Build Better Systems

    System validation at ARM
  • Introduction to AMBA 4 ACE

    This paper focuses on the AMBA® ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, Distributed Virtual Memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE™ software to run effectively, increasing system efficiency.

    Introduction to AMBA 4 ACE whitepaper
  • Quality of Service (QoS) in ARM Systems: An Overview

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in ARM® systems.

    Quality of Service (QoS) in ARM Systems whitepaper
  • QoS for High-Performance and Power-Efficient HD Media... - ARM

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

    QoS for High-Performance and Power-Efficient whitepaper

Useful whitepapers

System Validation at ARM: Enabling Partners to Build Better Systems

Introduction to AMBA 4 ACE

This paper focuses on the AMBA® ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, Distributed Virtual Memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE™ software to run effectively, increasing system efficiency. 

Quality of Service (QoS) in ARM Systems: An Overview

Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in ARM® systems. 

QoS for High-Performance and Power-Efficient HD Media... - ARM

Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

Introduction to QoS Virtual Networks (QVN)

This white paper explains a new mechanism for reducing the congestion in systems via QoS Virtual Networks. QVN makes system latency and bandwidth deterministic and predictable; preventing blocking in the interconnect by ensuring that a transaction can be accepted before it’s initiated.