CoreLink CCI-550

The Arm CoreLink CCI-550 Cache Coherent Interconnect

Getting Started

The Arm CoreLink CCI-550 Cache Coherent Interconnect provides full cache coherency between big.LITTLE processor clusters, Mali GPU, and other agents such as network interfaces or accelerators. It can support up to six ACE interfaces and six memory interfaces for the efficient movement of data across the SoC.

CCI-550 provides:

  • A trusted interconnect solution enabling multiple applications.

  • Optimized path to memory that enhances the user experience.

  • Highest efficiency coherent interconnect.

Specifications

 Features Details
 AMBA AMBA 4 ACE
 ACE Slave interfaces 1-6 for fully coherent processors including Arm Cortex and Mali GPU
 Memory and System master interfaces 1-6 memory interfaces
1-3 system interfaces
 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

  • TRM

  • CoreLink CCI-550 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-550 TRM
  • A guide on software optimization.

  • AMBA 4 ACE Specification

    CoreLink CCI-550 is built on the AMBA 4 ACE specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.

  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more
  • A program that is running on a desktop.

  • System Validation at Arm

    Enabling Partners to Build Better Systems

    Download
  • A program that is running on a desktop.

  • Introduction to AMBA 4 ACE

    This paper focuses on the AMBA ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, Distributed Virtual Memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE software to run effectively, increasing system efficiency.

    Download
  • A program that is running on a desktop.

  • Quality of Service (QoS) in Arm Systems: An Overview

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.

    Download
  • A program that is running on a desktop.

  • QoS for High-Performance and Power-Efficient HD Media... - Arm

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

    Download

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Community Forums

Not answered Request for advise on better ARM learning path for VLSI engineer 0 votes 23 views 0 replies Started 19 hours ago by chainastole Answer this
Suggested answer Cache Maintenance Transactions
  • AMBA
  • ACE
  • cache
  • Interface
 0 votes 225 views 3 replies Latest yesterday by Christopher Tory Answer this
Suggested answer How to handle clean operation in Data Cache
  • Cache coherency
 2 votes 236 views 1 replies Latest 2 days ago by Christopher Tory Answer this
Suggested answer How to handle Cache flush in ACE?
  • AMBA
  • ACE
  • cache
  • Interface
 1 votes 197 views 1 replies Latest 2 days ago by Christopher Tory Answer this
Not answered an a72 based embedded pcb. 0 votes 51 views 0 replies Started 8 days ago by MrGarvey Answer this
Not answered info please 0 votes 65 views 0 replies Started 9 days ago by Riccardo89 Answer this
Not answered Request for advise on better ARM learning path for VLSI engineer Started 19 hours ago by chainastole 0 replies 23 views
Suggested answer Cache Maintenance Transactions Latest yesterday by Christopher Tory 3 replies 225 views
Suggested answer How to handle clean operation in Data Cache Latest 2 days ago by Christopher Tory 1 replies 236 views
Suggested answer How to handle Cache flush in ACE? Latest 2 days ago by Christopher Tory 1 replies 197 views
Not answered an a72 based embedded pcb. Started 8 days ago by MrGarvey 0 replies 51 views
Not answered info please Started 9 days ago by Riccardo89 0 replies 65 views