CoreLink CCI-550

The Arm CoreLink CCI-550 Cache Coherent Interconnect

About CoreLink CCI-550

The Arm CoreLink CCI-550 Cache Coherent Interconnect provides full cache coherency between big.LITTLE processor clusters, Mali GPU, and other agents such as network interfaces or accelerators. It can support up to six ACE interfaces and six memory interfaces for the efficient movement of data across the SoC.

CCI-550 provides:

  • A trusted interconnect solution enabling multiple applications.

  • Optimized path to memory that enhances the user experience.

  • Highest efficiency coherent interconnect.

Applications

Application Icons

Request more information

Want more information on Arm CoreLink CCI-550? 

Contact us

CoreLink CCI-550 key features

Fully Coherent GPU support

1 to 6 ACE ports means CoreLink CCI-550 can enable a fully coherent GPU which simplifies software development. Hardware coherency enables shared virtual memory and removes the need for time-consuming software-managed cache maintenance.

Scalability

Highly scalable configuration means it can be designed for a wide range of applications from premium tablet down to smaller, cost-sensitive designs.

Increased Performance

A new microarchitecture was developed for the CoreLink CCI-550 snoop filter, resulting in a 2x snoop hit bandwidth that extends efficiency across the system.

Part of a Complete System Solution

TrustZone Secure Media Path to provide end to end protection for Ultra-HD content from the Mali GPU to memory.

Designed, tested and optimized with the latest Arm technology including Cortex and Mali processors, and CoreLink system IP.

CoreLink CCI-550 highlights

 Features Details
 AMBA AMBA 4 ACE
 ACE Slave interfaces 1-6 for fully coherent processors including Arm Cortex and Mali GPU
 Memory and System master interfaces

1-6 memory interfaces
1-3 system interfaces
 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

Useful Documentation

  • TRM

  • CoreLink CCI-550 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-550 TRM

  • AMBA 4 ACE Specification

    CoreLink CCI-550 is built on the AMBA 4 ACE specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs

  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more

  • System Validation at Arm

    Enabling Partners to Build Better Systems

    Download

  • Introduction to AMBA 4 ACE

    This paper focuses on the AMBA ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, Distributed Virtual Memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE software to run effectively, increasing system efficiency.

    Download

  • Quality of Service (QoS) in Arm Systems: An Overview

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.

    Download

  • QoS for High-Performance and Power-Efficient HD Media... - Arm

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

    Download

Useful whitepapers

System Validation at Arm: Enabling Partners to Build Better Systems

Introduction to AMBA 4 ACE

This paper focuses on the AMBA ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, Distributed Virtual Memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE software to run effectively, increasing system efficiency. 

Quality of Service (QoS) in Arm Systems: An Overview

Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems. 

QoS for High-Performance and Power-Efficient HD Media... - Arm

Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

Introduction to QoS Virtual Networks (QVN)

This white paper explains a new mechanism for reducing the congestion in systems via QoS Virtual Networks. QVN makes system latency and bandwidth deterministic and predictable; preventing blocking in the interconnect by ensuring that a transaction can be accepted before it’s initiated.