Getting Started

Infrastructure applications including networking, storage, and server have a wide range of compute performance and power requirements.  The Arm CoreLink CCN family is well suited to scale across the performance spectrum by supporting from 1 to 48 cores along with an integrated, configurable Level 3 system cache. The L3 system cache allows IO and accelerators to allocate memory on chip, offering reduced latency and power by minimizing accesses to external memory. The CCN family is optimized for the latest AMBA 5 CHI processors and memory controllers, and AMBA 4 ACE-Lite/AXI4 for IO interfaces.

  • CoreLink CCN-512 Cache Coherent Network Chip.
  • CoreLink CCN-512

    • Full coherency for up to twelve processor clusters (48 cores)
    • Supporting 1-32MB of L3 system cache for highest compute density

  • CoreLink CCN-508 Cache Coherent Network Chip.
  • CoreLink CCN-508

    • Full coherency for up to eight processor clusters (32 cores)
    • Supporting 1-32MB of L3 system cache for high performance compute and IO

  • CoreLink CCN-504 Cache Coherent Network Chip
  • CoreLink CCN-504

    • Full coherency for up to four processor clusters (16 cores)
    • Supporting 1-16MB of L3 system cache for the highest performance of 16 core systems

  • CoreLink CCN-502 Cache Coherent Network Chip.
  • CoreLink CCN-502

    • Full coherency for up to four processor clusters (16 cores)
    • Supporting up to 0-8MB of optional L3 system cache for small foot print cost sensitive applications

Product Comparison

Arm offers a range of CCN interconnects optimized for different size applications. Each product includes a wide configuration space allowing the SoC architect to optimize the interconnect to meet performance goals with the smallest possible area and power.

  CoreLink CCN-512 CoreLink CCN-508 CoreLink CCN-504
CoreLink CCN-502
Summary  Up to 12 cluster interconnect
(max processor bandwidth)
Up to 8 cluster interconnect
(high bandwidth) 
Up to 4 cluster interconnect
(high IO performance) 
Up to 4 cluster interconnect
(optimized for size) 
Performance Up to 225 GB/s
Up to 200 GB/s
Up to 150 GB/s
Up to 100 GB/s
Processors Up to 48 cores  Up to 32 cores  Up to 16 cores  Up to 16 cores 
DDR 1 to 4 channels  1 to 4 channels   1 to 2 channels   1 to 4 channels  
IO  Up to 24 AXI4/ACE-Lite Up to 24 AXI4/ACE-Lite  Up to 18 AXI4/ACE-Lite  Up to 9 AXI4/ACE-Lite 
Level 3 Cache  1-32 MB 1-32 MB  1-16 MB  0-8 MB 
System Size Large  Medium-Large  Medium  Small 
Example Applications Cloud applications, storage array network controller, Macro Base Station, and core networks.
Cloud applications, storage array network controller, Macro Base Station, and core networks.

Small enterprise solutions, cellular cell network, media content.
Home networks, home gateway, small cell base station, DSL modem, and web tier server.

CoreLink CCN System Examples

Server SoC with CoreLink CCN-512

Below is an example server configuration based on the CoreLink CCN-512.  It is designed to maximize compute density and well suited for web, cloud and big data analytic applications.  Some of the key features include:

  • Maximize compute density with 48x Cortex-A72, Arm's highest performance processor
  • Integrated 32MB of Level 3 System Cache for compute and IO
  • Up to 24 coherent IO ports for high bandwidth controllers such as 100Gb Ethernet and PCIe
  • 4 channels of x72 DDR4-3200 with CoreLink DMC-520

Networking SoC with CoreLink CCN-502

To meet the demands of increasing networking trafffic throughput and number of connected end points, system architects are looking to balance compute, storage and acceleration for a wide range of system design targets.  The CoreLink CCN-502 has been optimized for area and power making it the ideal interconnect for small to mid-range networking solutions.

  • Cortex-A72 processors provide the compute performance required of the Control Plane
  • Cortex-A53 processors provide efficient packet processing and IO throughput required of the Data Plane
  • Specialized DSPs, GPUs and other accelerators provide off-load engines for range of diverse needs such as security and layer 1 signal processing
  • Configurable CoreLink CCN-502 with flexible number of master interfaces, memory ports and optional Level 3 System Cache (0-8MB)


Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

Not answered When should APB slave Sample address/Data for read/write transaction from APB master? 0 votes 27 views 0 replies Started 2 days ago by arm_user Answer this
Not answered Timing simulation with ARM standard library 0 votes 29 views 0 replies Started 4 days ago by Yongchan Jeon Answer this
Not answered Can the ARM corrupt the timing on the AXI bus
  • SoC FPGA
  • Timing & Addressing
0 votes 51 views 0 replies Started 9 days ago by skbrown Answer this
Suggested answer Cycle Model Studio software
  • Cycle Model Studio
0 votes 170 views 1 replies Latest 15 days ago by Jason Andrews Answer this
Suggested answer why PSTRB signal in APB4 have four bits?
  • AMBA 4
0 votes 422 views 2 replies Latest 1 months ago by Colin Campbell Answer this
Not answered [ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface! 0 votes 174 views 0 replies Started 1 months ago by jaycekr Answer this
Not answered When should APB slave Sample address/Data for read/write transaction from APB master? Started 2 days ago by arm_user 0 replies 27 views
Not answered Timing simulation with ARM standard library Started 4 days ago by Yongchan Jeon 0 replies 29 views
Not answered Can the ARM corrupt the timing on the AXI bus Started 9 days ago by skbrown 0 replies 51 views
Suggested answer Cycle Model Studio software Latest 15 days ago by Jason Andrews 1 replies 170 views
Suggested answer why PSTRB signal in APB4 have four bits? Latest 1 months ago by Colin Campbell 2 replies 422 views
Not answered [ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface! Started 1 months ago by jaycekr 0 replies 174 views