CoreLink CMN-600

The Arm CoreLink CMN-600 Coherent Mesh Network

CMN-600 System Diagram.

CoreLink Coherent Mesh Network

The Arm CoreLink CMN-600 Coherent Mesh Network is designed for intelligent connected systems across a wide range of applications including networking infrastructure, storage, server, HPC, automotive, and industrial solutions.  The highly scalable mesh is optimized for Armv8-A processors and can be customized across a wide range of performance points. 

Notable highlights include:

  • Build more powerful infrastructure SoCs from edge to cloud.

  • 5x throughput uplift compared to today’s solution.

  • Coherent mesh interconnect with integrated agile system cache.


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CMN-600 highlights

Feature  Details  
AMBA specifications AMBA 5 CHI
Scalable mesh network Custom sizing and device placement  
Fully coherent CHI slave interfaces

1-32 fully coherent requesters, for example up to 128 Armv8-A processors

Agile System Cache 0MB-128MB shared between compute, accelerators, and IO
IO Coherent slave interface 1-96 IO interfaces
Memory and system master interfaces 1-8 memory interfaces
1-8 system interfaces
Coherency and snoop filter Integrated snoop filter reduces processor core snoops, and reduces system power
Coherent multichip links Extend coherency to multichip supporting the CCIX standard

CMN-600 key features

High performance, scalable coherent mesh 

The scalable mesh network can be customized to meet system performance and area requirements. The native AMBA 5 CHI network provides high-frequency, non-blocking data transfers between compute, accelerator, and IO to shared memory resources.  

  • Custom, automated design with CoreLink Creator
  • Minimum size less than 1mm2 in 16nm
  • Frequencies greater than 2.5GHz
  • Coherent multichip link extends coherency off-chip

CMN-Agile System Cache Diagram.

Agile system cache

Keeping data on-chip greatly improves performance and efficiency. The integrated agile system cache was designed to boost IO throughput workloads such as networking and storage.

  • Shared cache for compute, accelerators, and IO.
  • Intelligent cache stashing allows accelerators and IO peripherals to allocate critical data to any cache level.
  • Far atomic operations supported within the Agile System Cache to enable high frequency updates of shared data such as counters.  
  • Programmable on-chip scratch pad RAM partitioning options allow applications to lock down critical data structures such as counters, statistics, and tables.      

Optimized for system performance

The CoreLink CMN-600 has been designed with the CoreLink DMC-620 to provide the highest performance coherent backplane for Armv8-A systems from small, efficient access points to data center solutions maximizing compute density. Notable highlights include:

  • 7.5x more compute.
  • 5x higher throughput.
  • 50% lower latency.
  • Sustainable bandwidth exceeding 1TB/s.

Coherent Multichip Links

CoreLink CMN-600 coherent multichip links (CML) provide the capability of extending the high frequency, non-blocking AMBA 5 CHI protocol messages across multiple SoCs, enabling system designers to attach more compute or acceleration with a shared virtual memory.

The multichip links also supports CCIX, the open coherency standard that allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to acceleration devices including FPGAs, GPUs, network/storage adapters, intelligent networks and custom ASICs,

CoreLink Creator reduces SoC integration time

CoreLink Creator guides designers through the configuration and creation of an optimized and viable CoreLink CMN-600 interconnect fabric.

It addresses the most complex challenges associated with Interconnect configurability and assembly and enables a faster and easier design that produces a higher quality interconnect.

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