Getting Started

The Arm CoreLink CMN-600AE (Automotive Enhanced) Coherent Mesh Network is designed for high performance automotive systems across a wide range of applications including In-vehicle Infotainment (IVI), digital cockpit, Advanced Driver-Assistance Systems (ADAS) and autonomous driving systems.  The highly scalable mesh is optimized for Armv8-A processors and can be customized across a wide range of performance points.

CMN-600AE is part of Arm's Safety Ready program, a collection of products across the Arm portfolio that have been through various and rigorous levels of functional safety systematic flows and development.

Notable highlights include:

  • Ability to build more scalable, power efficient automotive SoCs from ADAS to autonomous driving.

  • Coherent mesh interconnect with integrated agile system cache and integrated coherent multichip support.

  • Integrated resilience and functional safety features, with enhanced device management capabilities. 

  • Extended safety documentation package (systems up to ASIL D).


Specifications

Feature  Details  
AMBA specifications AMBA 5 CHI with extensions for interface protection 
Scalable mesh network Custom sizing and device placement
Fully coherent CHI slave interfaces 1-8 fully coherent requesters, for example up to 64 Armv8-A processors
Agile system cache 0MB-32MB shared between compute, accelerators, and IO
IO coherent slave interface 1-24 IO interfaces
Memory and system master interfaces 1-4 memory interfaces
1-4 system interfaces
Coherency and snoop filter Integrated snoop filter reduces processor core snoops, and reduces system power
Coherent multichip links Extend coherency to multichip supporting the CCIX standard
Integrated resilience and functional safety Integrated RAM with ECC, CRC protection on transport, transaction error detection and memory protection unit

CMN-600AE key features

Automotive enhanced scalable coherent mesh

The CMN-600AE is designed to meet the automotive safety requirements for building high performance ASIL B to ASIL D systems. It uses a highly optimized architecture that implements redundancy, while minimizing area using protected shared memories. The CMN-600AE provides fault detection and correction features that meet the highest safety requirements of systems up to ASIL D, including:

  • Integrated resilience and functional safety with ECC on shared integrated RAMs, CRC protection on transport, timeouts, memory protection unit and resource isolation.
  • Enhanced device management capabilities with fault management unit.
  • Extended safety documentation package (for systems up to ASIL D).

High performance scalable coherent mesh

The scalable mesh network can be customized to meet system performance and area requirements. The native AMBA 5 CHI network provides high-frequency, non-blocking data transfers between compute, accelerator, and IO to shared memory resources. 

  • Custom, automated design with CoreLink Creator. 
  • Minimum size less than 1mm² in 16nm. 
  • Frequencies greater than 2.5GHz. 
  • Coherent multichip link extends coherency off-chip.

Agile system cache

Keeping data on-chip greatly improves performance and efficiency. The integrated agile system cache was designed to boost high throughput workloads, such as computer vision processing and neural networks. 

  • Shared cache for compute, accelerators, and IO. 
  • Intelligent cache stashing allows accelerators and IO peripherals to allocate critical data to any cache level. 
  • Far atomic operations supported within the Agile System Cache to enable high frequency updates of shared data such as counters.   
  • Programmable on-chip scratch pad RAM partitioning options allow applications to lock down critical data structures such as counters, statistics, and tables.

Coherent Multichip Links

The Coherent Multichip Links (CML) of the CMN-600AE allow the extension of the high frequency, non-blocking AMBA 5 CHI protocol messages across multiple SoCs, enabling system designers to attach more compute or acceleration with a shared virtual memory.

The multichip links also support CCIX, the open coherency standard that allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to acceleration devices including FPGAs, GPUs, network/storage adapters, intelligent networks and custom ASICs. For more information, see www.ccixconsortium.com.

CoreLink Creator reduces SoC integration time

CoreLink Creator guides designers through the configuration and creation of an optimized and viable CMN-600AE interconnect fabric.

It addresses the most complex challenges associated with interconnect configurability and assembly and enables a faster and easier design that produces a higher quality interconnect.

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Forums

Not answered When should APB slave Sample address/Data for read/write transaction from APB master? 0 votes 28 views 0 replies Started 3 days ago by arm_user Answer this
Not answered Timing simulation with ARM standard library 0 votes 32 views 0 replies Started 5 days ago by Yongchan Jeon Answer this
Not answered Can the ARM corrupt the timing on the AXI bus
  • SoC FPGA
  • Timing & Addressing
0 votes 53 views 0 replies Started 11 days ago by skbrown Answer this
Suggested answer Cycle Model Studio software
  • Cycle Model Studio
0 votes 174 views 1 replies Latest 16 days ago by Jason Andrews Answer this
Suggested answer why PSTRB signal in APB4 have four bits?
  • AMBA 4
0 votes 427 views 2 replies Latest 1 months ago by Colin Campbell Answer this
Not answered [ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface! 0 votes 178 views 0 replies Started 1 months ago by jaycekr Answer this
Not answered When should APB slave Sample address/Data for read/write transaction from APB master? Started 3 days ago by arm_user 0 replies 28 views
Not answered Timing simulation with ARM standard library Started 5 days ago by Yongchan Jeon 0 replies 32 views
Not answered Can the ARM corrupt the timing on the AXI bus Started 11 days ago by skbrown 0 replies 53 views
Suggested answer Cycle Model Studio software Latest 16 days ago by Jason Andrews 1 replies 174 views
Suggested answer why PSTRB signal in APB4 have four bits? Latest 1 months ago by Colin Campbell 2 replies 427 views
Not answered [ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface! Started 1 months ago by jaycekr 0 replies 178 views