The Arm CoreLink Network Interconnect offers highly configurable topology with Network on Chip (NoC)-like properties that enable you to build high performance, optimized, AMBA-compliant SoC connectivity. CoreLink Network Interconnect is configurable across a wide range of applications from a single bridge component, for example an AHB to AXI protocol bridge, to a complex infrastructure that consists of up to 128 masters and 64 slaves in a combination of different AMBA protocols.

  • CoreLink NIC-450 Network Interconnect Chip.
  • CoreLink NIC-450

    • Library of key interconnect IP that enables designers to build a scalable and configurable network interconnect
    • Available with a new tooling automation flow using CoreLink Creator that employs algorithms to accelerate configuration based on design requirements
    • Enables integrated tooling environment using CoreLink Creator and Socrates DE (licensed separately) for configuring complex interconnect subsystem designs.
    • Includes all NIC-400 features
  • CoreLink NIC-400 Network Interconnect Chip.
  • CoreLink NIC-400

    • Fully configurable, hierarchical, low latency, low power connectivity for AMBA 4 AXI4, AXI3, AHB-Lite and APB interfaces.
    • Scalable for multiple applications from simple single core designs, up to large coherent systems as a companion to CoreLink CCI and CCN coherent interconnects.

    NIC-400 TRM

NIC-450 and CoreLink Creator

CoreLink Creator with its harvesting flows and enhanced tooling environment provides significant improvements to configure NICs, which decreases time to market.

Functional enhancement in NIC-400r1 with QVN-terminate feature to resolve head-of-line blocking when accessing DRAM provide:

  • Improved support for QVN with DMC controllers using sideband QOSACCEPT signaling, supported in DMC-500 and other 3rd party DMC providers.

  • CPU latency reduction with QoS enhancements, designed and tested with Arm memory controllers such as CoreLink DMC-500.

NIC-450 Library of Interconnect IP

Network Interconnect NIC-400
Advanced Quality of Service QoS-400
 Virtual Networks QVN-400
 Thin Links TLX-400
 AMBA Domain Bridge ADB-400
 AXI-to-AHB Bridge XHB-400
 Low-power distributor LPD-500

Product Features

Configurable by Design

The CoreLink Network Interconnect is a highly configurable low latency IP that can be optimized to suit the requirements of a complex SoC using the AMBA protocols. 

  • CoreLink QoS-400 Advanced Quality of Service option provides dynamic bandwidth or latency controlled regulators for the efficient and intelligent management of traffic in complex multimaster designs.

  • CoreLink QVN-400 QoS Virtual Networks prevent cross-stream or head-of-line blocking through a priority-driven allocation of buffer space to different virtual channels in both the interconnect and the dynamic memory controller (CoreLink DMC-400 or DMC-500).

  • CoreLink TLX-400 Thin Links option for NIC-400 packetized AXI4 connections, for transmission between switches over fewer signals to reduce wiring congestion and ease timing closure.

  • Accelerated configuration with Arm CoreLink Creator tooling.

Companion to Cache Coherent Interconnects

CoreLink NIC-400 can be used together with the CoreLink CCN-504 Cache Coherent Network or the CoreLink CCI-400 Cache Coherent Interconnect to extend I/O coherency to larger numbers of masters.

Flexible Topology Adapting to System Requirements

A wide configuration space and flexible topology allows the interconnect to adapt to the system requirements and SoC floor plan. The product can scale from a simple one input one output bridge, all the way up to an SoC wide interconnect with over 100 interfaces. Routing of requests and data is by AXI switches within the fabric. Each link and switch is configurable in width from 32 to 256 bits, allowing the system architect to minimize the number of wires and the interconnect area to meet performance requirements. Flexible data buffering options allow efficient packing and transport of data when changing bus widths.

Advanced Timing Closure Options for High Frequency

Timing closure on small geometry, large SoC design can be accelerated with flexibility on timing closure options within the interconnect. The Network Interconnect offers high flexibility on register placement allowing fine grain tuning in the trade-off between clock speed and latency. Register stages can be configured per-channel and per-direction to isolate long paths.

Support for the Latest AMBA Protocols

Interfaces are fully configurable between AXI4, AXI3, AHB-Lite and APB. Connectivity to cache coherent systems is supported with the CoreLink CCI and CCN families.