Overview

Arm CoreSight architecture documents consist of a set of architectural specifications to support the integration of various IP components in a standardised way, thus ensuring support from the tooling ecosystem. 

  • Architecture Specifications

    • Embedded Trace Macrocell Architecture Specification
    • CoreSight Program Flow Trace Architecture Specification
    • CoreSight Architecture Specification

    CoreSight Architecture Spec
  • Arm Debug Interface (ADI) architecture v6

    • Access to embedded debug functionality


    Arm Debug Interface (ADIv6)
  • Arm Debug Interface (ADI) architecture v5

    • Access to embedded debug functionality


    Arm Debug Interface (ADIv5)
  • High Speed Serial Trace Port (HSSPT)

    • Lower ASIC pin count
    • Increase possible bandwidth
    • Reduce silicon area

    HSSTP Architecture Spec
  • Serial Wire Debug

    • 2-pin debug port
    • Low pin count
    • High-performance alternative to JTAG

    Discover more...

Arm Debug Interface

ADIv5 defines a standard debug interface for debug components in an embedded SoC. This specification is written for system designers and engineers who are specifying, designing or implementing a debug interface to the ADIv5 architecture specification.

Embedded Trace Macrocell Architecture Specification

An Embedded Trace Macrocell (ETM) is a real-time trace module providing instruction and data tracing of a processor. An ETM is an integral part of an Arm CoreSight debug and real-time trace solution.

This specification describes the Arm Embedded Trace Macrocell (ETM) architecture. All ETMs conform to a version of this architecture that covers the following areas of functionality:

  • The Programmer’s Model
  • The Trace Port Protocol
  • The Physical Interface

CoreSight Program Flow Trace Architecture Specification

A Program Trace Macrocell (PTM) is a real-time trace module providing instruction tracing of a processor. A PTM is an integral part of an Arm CoreSight debug and real-time trace solution.

This specification describes the Program Flow Trace Macrocell (PTM) architecture. All PTMs conform to a version of this architecture that covers the following areas of functionality:

  • The Programmer’s Model
  • The Trace Port Protocol
  • The Physical Interface

  • CoreSight Architecture Specification

    The CoreSight architecture provides a set of standard interfaces and programmer model views enabling partners to define CoreSight components and integrate them within the CoreSight infrastructure.

    High Speed Serial trace Port  (HSSTP)

    The HSSTP architecture specification specifies a Serial Transmit Port (STP) as a replacement for an existing parallel data output port, suitable for transmitting high bandwidth data off-chip such as from the CoreSight solution.

    Resources