Overview

Arm® CoreSight™ components provide all the infrastructure required to debug, monitor and optimize the performance of a complete System on Chip (SoC) design.

  • CoreSight SoC-600

    CoreSight SoC-600 builds on the capabilities of SoC-400 by adding debug and trace over any functional interface, and greater trace bandwidth.

    CoreSight SoC-600
  • CoreSight SoC-400

    Provides configurable CoreSight SoC components for the generation of debug, trace, cross-trigger and time-stamping functionality. Design productivity is achieved through the use of CoreSight Creator, its companion IP integration tooling solution

    CoreSight SoC-400
  • System Trace Macrocell

    The System Trace Macrocell enables real-time instrumentation of software without altering system behaviour, offering for instance _fprint_ functionality

    System Trace Macrocell
  • Trace Memory Controller

    Trace Memory Controllers can be configured as trace buffers or FIFOs, as well as serving as trace sinks for routing trace data on or off chip

    Trace Memory Controller
  • CoreSight ELA-500 Embedded Logic Analyzer

    The Embedded Logic Analyzer provides on-chip signal trace capabilities for the identification of faults not otherwise easily identifiable with traditional debug methods. Thanks to its small silicon footprint, multiple instances can be used. 

    CoreSight ELA-500
System diagram with CoreSight debug and trace callouts

Highlights

CoreSight System IP enables embedded software developers and SoC designers to develop high performance systems, both software and hardware, while decreasing development time and risks.

The CoreSight product portfolio is supported by Arm DS-5 Development Studio and Keil MDK, as well as over 25 other debug and performance analysis tools worldwide, giving product development teams the assurance that their product will be widely supported.

CoreSight SoC-600

Arm CoreSight SoC-600 offers the most comprehensive library for the creation of debug and trace solutions. This includes debug access, trace routing and termination, cross-triggering and time stamping.

Architectural changes simplify and standardise access into debug memory space, enabling protocol based debug access though existing functional interfaces.

Reliance on a protocol that is agnostic of the physical link, ensures that solutions built around CoreSight SoC-600 are portable and scalable, avoiding the limitations associated with point solutions.

CoreSight SoC-400

CoreSight SoC-400 provides a comprehensive library of debug and trace configurable components, from debug access to cross triggering and timestamp distribution.  Configuration scripts are also supplied, and for those looking for a productivity boost, CoreSight Creator offers graphical IP integration and configuration functionality.

All components can be grouped into one of the categories listed below:

  • Control and Access Components: Provide access to other debug components and control of debug behavior.
  • Sources: Generate trace data for output through the ATB.
  • Links: Provide connection, triggering, and flow of trace data.
  • Sinks: End points for trace data on the SoC.
  • Timestamp: Generates and transports timestamps across the SoC.
  • Triggering: Distributes trigger signals between processing elements.

System Trace Macrocell

The System Trace Macrocell (STM) enables real-time instrumentation of software without altering system behavior, as well as real-time analysis of the platform behavior and performance.

The STM is a trace source that is integrated into a CoreSight system. This instrumentation is made up of memory-mapped writes to the STM Advanced eXtensible Interface (AXI) slave, which are then formatted into trace data and output over an ATB interface. For configuration purposes, the STM is connected to the Debug APB so that it can be accessed by off-chip and on-chip debug agents.

Trace Memory Controller

The Trace Memory Controller (TMC) provides trace sink functionality for routing trace on/off chip, as well as offering intermediate trace storage.

Three main configuration options allow it to function as:

  • A buffer - this enables trace to be stored in a dedicated SRAM.
  • A FIFO - the functionality of this configuration is a superset of the functionality of the buffer configuration.
  • A router - this enables trace to be routed over an AXI bus to system memory or to any other AXI slave.

CoreSight ELA-500 Embedded Logic Analyzer

The ELA-500 Embedded Logic Analyzer can be connected to Arm and 3rd party IP components to ensure faster silicon debug when visibility of low level signals is needed. Each ELA can monitor up to 12 groups of up-to 128 signals to detect the states leading to lock-ups and data corruption. For instance, it can provide visibility of CPU load, stores, speculative fetches, cache activity and transaction lifecycle - properties that are not visible with existing ETM trace of instructions or other common debug methodologies. This way, an ELA can spot data corruptions as they occur, capturing the cause, whereas conventional timeouts are too late and causation events are often lost.

The ELA-500 Embedded Logic Analyzer is a Design for Debug component that is integrated onto silicon for the purpose of debugging hardware-related issues. Debug signals are connected from an IP component to the ELA-500, which compares the signals with a target value and drives actions. There is an optional trace capability that can be used to generate a history of the debug signals at any point in time.

For ease of use, the ELA can also be programmed externally through Arm's DS-5 via a Debug & Trace Sevice Layer (DTSL). 

The culmination of decades of development in debug and trace IP – Arm® CoreSight™ SoC-600 offers the most comprehensive library for the creation of debug and trace solutions. This includes debug access, trace routing and termination, cross-triggering and time stamping.

Architectural changes simplify and standardise access into debug memory space, enabling protocol based debug access though existing functional interfaces.

Reliance on a protocol that is agnostic of the physical link, ensures that solutions built around CoreSight SoC-600 are portable and scalable, avoiding the limitations associated with point solutions.