About CoreSight SoC-400
The SoC-400 library offers configurable components to meet the exact requirements of your system, from small to multiprocessor Cortex-A class designs. With over 20 years of development behind it, CoreSight SoC-400 is the standard for Arm-based SoC designs and enjoys broad support from the tooling ecosystem.
Safeguard against costly delays.
The industry standard for debug and trace IP.
Comprehensive library of configurable on-chip debug and trace components.
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CoreSight SoC-400 provides configurable components for the creation of all four main aspects of debug and trace functionality:
- Debug access.
- Trace generation, manipulation, and output.
- Cross triggering.
- Time stamping.
Configurable components that are offered in CoreSight SoC-400 can broadly be classified into:
- Debug access, to build the interface between an external debugger (using, for example, JTAG or SWD) and processors, memory systems, and other CoreSight components.
- Trace, to generate and end trace buses, and provide the links between source and sink.
- Cross-triggering, to allow components to control actions from and to other components.
- Clocks, resets, and power management.
- Time stamp, to generate and distribute time stamps across components.
Also, Arm provides separate trace components for the generation of system trace, the System Trace Macrocell (STM), and the management of intermediate and termination of trace buses, Trace Memory Controller (TMC).
• Robust design
• Faster bring up means a reduced time-to-market
• Improved reliability
• Hardware/Software co-development via debugger in simulation and emulation
• Performance profiling
• Performance optimization (both hardware and software)
• Reduced bug cost
• Reduced time to market
CoreSight SoC-400 Technical Reference Manual
For system designers, system integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.CoreSight SoC-400 TRM
Technical Introduction to CoreSight
Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.Download white paper
Introduction to CoreSight SoC-400
This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.Watch video
Better trace for better software with Arm CoreSight
This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.Download white paper
Low pin-count debug interfaces for multi-device systems
This white paper examines some alternatives to JTAG as a debug interface, and concludes that a Serial Wire Debug interface can be delivered with lower pin-count and higher performance, and at the same time, maintain support for multiprocessor systems and interoperability with test.Download white paper
Key steps to create a debug and trace solution for an Arm SoC
The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.Download white paper
Documents and blogs that are useful when designing Arm-based SoCs.