Information on the future of debug: CoreSight

Getting Started

The culmination of decades of development in debug and trace IP – Arm CoreSight SoC-600 offers the most comprehensive library for the creation of debug and trace solutions. This includes debug access, trace routing and termination, cross-triggering and time stamping.

Architectural changes simplify and standardise access into debug memory space, enabling protocol based debug access though existing functional interfaces.

Reliance on a protocol that is agnostic of the physical link, ensures that solutions built around CoreSight SoC-600 are portable and scalable, avoiding the limitations associated with point solutions.

Key benefits include:

  • Debug access available and accessible throughout the product lifecycle, from production and manufacture, to remote access in the field
  • Remote debug access (e.g. via Ethernet or wirelessly)
  • Increased data bandwidth for improved system visibility

Total cost of ownership (TCO) is reduced thanks to a combination of greater system visibility and a reduction in operational costs. 

Learn more about CoreSight SoC-600

New DAP architecture

The new Debug Access Port (DAP) architecture introduces standard APB connectivity between Debug Port (DP) and Access Port (AP), making it possible to have multiple DPs connected to multiple APs.

Benefits include:

  • Multiple debug agents can simultaneously access debug memory space (e.g. for concurrent external and self-hosted access)
  • Interface peripherals (such as USB and PCIe) share a common access to APs, together with any existing JTAG DP or resident software
  • Self-hosted, cross CPU debug access
DAP Architecture Diagram.

High trace bandwidth

CoreSight SoC-600 introduces enhanced Embedded Trace Router (ETR) functionality out-of-box. In additional to removing the need for a separate Trace Memory Controller (TMC) license, enhancements to the Embedded Trace Router (ETR) configuration make it possible to supply a trace interface with four times the amount of bandwidth previously possible.

In practice, each ETR configuration can supply a trace output port with up to 100Gbps, should the link be capable of such rates.

As the total amount of trace bandwidth increases, so does the visibility into time correlated events across the SoC, from CPU instructions to system trace (STM), as well as paving the way for bus tracing.

Further improvements have been made to the handoff of buffer contents between interface controllers and ETR. Reliance on a CPU to manage such traffic is significantly reduced.

The ETR now also signals the debugger when trace has been flushed. Capabilities of Embedded Trace Buffer (ETB) and Embedded Trace FIFO (ETF) remain unchanged from the standalone TMC.

System design choices

Broadly speaking, CoreSight SoC-600 systems can be built to have the link protocol hosted by either a main CPU or a dedicated one. There are pros and cons associated with either approach, which are summarized below.

Protocol on dedicated CPU: this approach comes at a cost of additional dedicated resources, however, it is the least intrusive approach and provides bare metal debug capabilities.

Protocol on main CPU: this approach does not require additional hardware, yet it is invasive and relies on CPU not being halted.


Security

Debug access extended to functional IO needs to maintain the same level of security as offered through a JTAG connection. CoreSight SoC-600 continues to offer security control on the DAP side, now extended to accesses over protocol. 

More than an IP library

CoreSight SoC-600 offers much more than just configurable IP. In an effort to support the creation of entire end-to-end solutions, the following items have been developed alongside the IP library and will be made available to IP licensees, tools developers and application developers.

  • Debug and trace protocol

    Availability of a standardised protocol and API between debugger and SoC is key to accelerate development of CoreSight SoC-600 solutions and in avoiding fragmentation into multiple custom protocols and associated efforts.

  • Open source Linux drivers

    Availability of software drivers is critical to self-hosted debug. Arm’s developed drivers will be supplied.

  • Productivity tools
    CoreSight SoC-600 is a library of components that requires stitching into a topology appropriate to the design goals. This flow can be time consuming and requires a deep understanding of the underlying CoreSight architecture. CoreSight Creator automates the process of creating CoreSight compliant designs, greatly reducing development cycles.

Enhancements across the SoC library

As part of an extensive effort to update the entire library, all elements in CoreSight SoC-600 have been refreshed with the aim of improving the performance range of supported future CPUs.

Similarly, significant effort has gone towards reducing logic area and power consumption by offering better finer control over which features are implemented.

For improved power management, all power aware elements in the SoC-600 library now benefit from a standardised Low Power Interface (LPI) via a Q-channel interface

Tools support

CoreSight SoC-600 based SoCs will benefit from support in Arm DS-5 Development Studio, as well as from a number of independent tools vendors.

Learn about customer success stories

Want to know more about SoC-600 and our customer success stories? Learn more by clicking the link below.

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Not answered When should APB slave Sample address/Data for read/write transaction from APB master? 0 votes 28 views 0 replies Started 3 days ago by arm_user Answer this
Not answered Timing simulation with ARM standard library 0 votes 32 views 0 replies Started 5 days ago by Yongchan Jeon Answer this
Not answered Can the ARM corrupt the timing on the AXI bus
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Suggested answer Cycle Model Studio software
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Suggested answer why PSTRB signal in APB4 have four bits?
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Not answered [ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface! 0 votes 178 views 0 replies Started 1 months ago by jaycekr Answer this
Not answered When should APB slave Sample address/Data for read/write transaction from APB master? Started 3 days ago by arm_user 0 replies 28 views
Not answered Timing simulation with ARM standard library Started 5 days ago by Yongchan Jeon 0 replies 32 views
Not answered Can the ARM corrupt the timing on the AXI bus Started 11 days ago by skbrown 0 replies 52 views
Suggested answer Cycle Model Studio software Latest 16 days ago by Jason Andrews 1 replies 174 views
Suggested answer why PSTRB signal in APB4 have four bits? Latest 1 months ago by Colin Campbell 2 replies 427 views
Not answered [ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface! Started 1 months ago by jaycekr 0 replies 178 views