CoreSight STM-500 System Trace Macrocell

The Arm CoreSight STM-500 System Trace Macrocell.

About CoreSight STM-500

The Arm CoreSight System Trace Macrocell (STM) is a trace source that enables real-time instrumentation of software with no impact on system behavior or performance. For software, system and hardware engineers, visibility of the complete system is now critical. This is due to the need to deliver high performance, power optimized systems in shorter development cycles.

The Arm CoreSight System Trace Macrocell (STM) extends low-cost real-time visibility of software and hardware execution to all software developers. In particular application and kernel developers, enabling rich, optimized and low power software on Arm processor-powered devices across the whole supply chain.

Highlights

The CoreSight STM-500 enables low latency and high-bandwidth printf-style debug, offering developers more visibility into their software without impacting system behavior.

Key features

STM offers software instrumentation that is: 

  • Low latency.
  • High bandwidth.
  • Non-intrusive.
  • Time-stamped.
  • Scalable to a multiprocessor system, up to 64k stimulus ports, and 128 masters.

 Low latency, high performance software instrumentation

The STM enables low latency and high bandwidth printf-style debug capability, that gives developers more visibility into their software. It does this without altering the system behaviour, making it easier to develop and optimize software on Arm processor-based systems.

System performance tuning and debug

To system developers, the STM provides timing-accurate on-chip visibility of the software and hardware interaction. This enables Arm silicon partners and OEMs to optimize their SoCs even further and bring their platforms to market faster.

An industry standard

The CoreSight System Trace Macrocell offers an industry standard across all markets for system visibility. All major tool vendors will support Arm system trace macrocells.

STM complements the industry standard Embedded Trace Macrocell (ETM) and is compliant with MIPI System Trace specification.

Arm System Trace for Cortex-A and Cortex-R Processor-based SoC

The CoreSight System Trace Macrocell is architected to provide low latency and high bandwidth real-time system instrumentation required for real-time and application based platforms.The Arm STM supersedes the Instrumentation Trace Macrocell (ITM) for these applications; for Cortex-M series processor-based devices, ITM remains the preferred solution.

Two variants of the System Trace Macrocell exist:

  • STM-101 for 32-bit systems.
  • STM-500 for 64-bit systems, backward compatible to 32-bit.

STM Key performance characteristics

  • Designed to operate at system frequency for Cortex-A and Cortex-R processor-based SoC (e.g. at least 400MHz on 65LP)
  • 32-bit data trace path (32-bit AXI interface, 32-bit ATB interface) for high bandwidth and low latency system instrumentation
  • Fully memory-mapped software stimulus supporting 65,536 stimulus ports and 128 masters
  • Compatible with the latest MIPI System Trace protocol

Useful Documentation

  • CoreSight STM-500 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CoreSight STM-500 TRM
  • CoreSight technical introduction

    Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.

    Download whitepaper
  • Introduction to CoreSight SoC-400

    This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.

    Watch video
  • Better trace for better software with Arm CoreSight

    This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.

    Download whitepaper
  • Low pin-count debug interfaces for multi-device systems

    This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, and maintain support for multiprocessor systems and interoperability with test.

    Download whitepaper
  • Key steps to create a debug and trace solution for an Arm SoC

    The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.

    Download whitepaper