The CoreLink DMC-520 and DMC-620 Dynamic Memory Controller are designed to provide a high-performance solution for SoC deployed in infrastructure applications including servers, high-performance computing (HPC), and networking. The CoreLink DMC-520 is optimized to work with the CoreLink CCN-5xx family of Cache Coherent Network products using native AMBA® 5 CHI. CoreLink DMC-520 provides a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L, and DDR4 DRAM along with full support of UDIMM, RDIMM, and LRDIMM. Enterprise class RAS (Reliability, Availability, and Serviceability) features such as ECC for x72 DRAM, TrustZone® security, and end-to-end QoS are integral components of this memory controller. The CoreLink DMC-520 is integrated with industry-standard DFI 3.1 DDR PHYs using 1:1, 1:2 or 1:4 configurable DFI frequency ratios.
For High-end Infrastructure Systems
The Corelink DMC-620 is a superset of the DMC-520 in terms of the features supported, and is optimized to work with CoreLink CMN-600 interconnect using the CHI system interface protocol while also maintaining backwards compatibility with CoreLink CCN-5xx family of products. It has extended virtual rank support to enable addressing of very high-density 2H, 4H, or 8H 3DS DRAM devices. With this support, a single channel of CoreLink DMC-620 can address up to 1TB of DRAM memory, providing system designers with sufficient headroom for growing the DRAM footprint of their high-end systems. The Corelink DMC-620 offers support for sophisticated RAS features such as end-to-end data parity protection, corrected data writeback, retry on uncorrectable ECC errors, memory scrubbing, and standardized error reporting. It supports both the standard SECDED (Single Error Correct Multiple Error Detect) and advanced symbol-based ECC for correcting complete failure of a x4 memory device.
Both DMC-520 and DMC-620 have been proven interoperable with multiple 3rd party DFI-compliant DDR PHYs.
For Mobile and Consumer Systems
The CoreLink DMC-500 is optimized for ARM systems to deliver high performance and power efficient access to LPDDR4 x16 and LPDDR3 x32 memory. The CoreLink DMC-500 offers excellent integration with the CoreLink interconnect products, sharing QoS mechanisms and power management. End-to-end QoS for each of CPU, GPU, and other bus masters guarantees performance while increasing memory and wire utilization, as well as TrustZone technology Address Space Control that provides security across the system. A single DFI 4.0 memory interface offers 128-bit DFI data width at speeds of up to 533MHz. PHY management is included as part of the memory interface, allowing for faster integration to the memory subsystem.
|Feature||CoreLink DMC-500||CoreLink DMC-520||CoreLink DMC-620|
||2x AXI4 interfaces
||1x for direct connection to CCN products using AMBA 5 CHI
||1x for direct connection to CCN-5xx or CMN-600 products using AMBA5 CHI|
|System Data Width
||256-bit or 128 bit|
||Single interface per channel connected to PHY with DFI 4.0
||Single interface per channel connected to PHY with DFI 3.1
||Single interface per channel, connected to PHY with DFI 4.0|
||LPDDR3 and LPDDR4
||DDR3, DDR3(L) and DDR4 with support for UDIMM, RDIMM and LRDIMM
||DDR3, DDR3(L), and DDR4 with support for UDIMM, RDIMM, LRDIMM, and NVDIMM-N|
||x16 or x32 bit
||x72 or x40 bit (including 8-bit ECC)
||x72 or x40 bit (including 8-bit ECC)|
||SECDED or symbol-based ECC
||SECDED or symbol-based ECC|
|Maximum DDR Speed
||Up to LPDDR3-2133 or LPDDR4-4267 Mbps
||Up to DDR4-3200 Mbps
||Up to DDR4-3200 Mbps|
|# Chip Selects
|QoS||QoS based scheduling algorithm through Cache Coherent Interconnect
||QoS based scheduling algorithm, QVN support, non-blocking paths to DRAM through Cache Coherent Network
||QoS based scheduling algorithm, QVN support, non-blocking paths to DRAM through Coherent Mesh Network|
|Latency||QoS mechanisms ensure critical masters can achieve minimum latency
|Low Power||All DRAM power modes supported and hierarchical clock gating throughout the DMC