AMBA System Controllers
AMBA system controllers are a collection of controller IP that Arm offers. These controllers are for Direct Memory Access (DMA), Level 2 Cache, TrustZone, and peripherals. These controllers are low-power, high-performance IP cores that perform critical tasks within the AMBA system. Designed for optimal compatibility with Arm Cortex, Mali multimedia, and CoreLink System IP, they are the natural complement to interconnect and memory controllers.
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Efficient use of DMA can significantly improve system performance in multiple dimensions. For example, using a DMA controller can offload a processor and either reduce power consumption, or boost the processor performance, or a combination of both. AMBA DMA controllers are designed to complement both high-end and energy-efficient systems. They provide a centralized DMA processing capability that is high performance and highly flexible, and at the same time, is area efficient. Key product offerings for DMA controllers are:
CoreLink DMA-330: The DMA-330 is a high-performance DMA controller that can boost the performance and reduce the power consumption in AXI systems. The DMA-330 is a highly configurable device to support a wide range of applications and architectures. The DMA-330 is programmable to support scatter-gather, memory to memory, peripheral to memory, and memory to peripheral transfers, run-from-reset, security on channels, interrupts, and peripherals.
Click to view the DMA-330 TRM.
PrimeCell Micro DMA-230: The DMA-230 is a low gate count (3-10k gates) micro-DMA engine targeting Cortex-M3 systems and other low-power and cost-sensitive applications. The device offers excellent performance at low gate count and all the code is stored in system RAM rather than in registers. Using this component enables Cortex-M1 and Cortex-M3 based systems to remain low cost through reduced gate count and enabling scaling down the frequency of the processor in the system for reducing overall power consumption.
Click to view the DMA-230 TRM.
Processor to off-chip memory communication has become the performance bottleneck in many SoCs. Level 2 cache controllers improve processor performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced processor demands on the off-chip memory bandwidth free up that resource for other masters. Level 2 cache controllers also contribute significantly to power efficiency because on-chip accesses are typically an order of magnitude lower in power when compared to going off-chip. CoreLink level 2 cache controllers, that are embedded in the processor or delivered as standalone components, are designed alongside the processor to match the processor requirements and easily integrate into AMBA AXI or AHB interconnects.
The CoreLink L2C-310 cache controller is a high-performance, AXI level 2 cache controller that is designed and optimized to address Arm AXI processors, such as the Cortex-A9, Cortex-A5, Cortex-R4, Cortex-R5, Cortex-R7, Arm11MPCore, Arm1176, and Arm1156. The Mali-200 graphics processor can also benefit from this product.
Click to view the L2C-310 TRM.
TrustZone system IP blocks support the Arm TrustZone system-wide approach to security for preventing access by malicious software to memory regions and peripherals such as keyboards and screens. There are three products in this category:
TZC-400 - CoreLink TZC-400 TrustZone Address Space Controller extends on-chip security to protect multiple regions of external memory from software attacks. TZC-400 includes 'fast path' to hide look up latency and has AMBA 4 ACE-Lite and AXI4 support. It is configurable to protect up to 32 different regions in memory, and is compatible with CCI-400, NIC-400, and DMC-400 product families.
Click to view the TZC-400 TRM.
BP147 – PrimeCell BP147 TrustZone Protection Controller enables the Secure and Non-secure worlds to safely share peripherals. It supports an APB interface that is common to most I/O peripherals.
Click to view the BP147 TRM.
BP141 – PrimeCell BP141 TrustZone Internal Memory Wrapper manages a single Secure region with on-chip SRAM memory.
Click to view the BP141 TRM.
Arm System IP also supports various general-purpose peripheral controllers. These products augment the standard IP solutions for customers adopting Arm in various systems. The following is a list of peripheral controllers available:
PL011 is a synthesizable Universal Asynchronous Receiver Transmitter (UART) serial port controller.
Click to view the PL011 TRM.
PL022 is a synthesizable Single-wire Peripheral Interface (SPI) controller, master and slave. The PL022 supports Motorola SPI, TI SSI, and Microwire.
Click to view the PL022 TRM.
PL061 is a synthesizable General Purpose Input-Output (GPIO) controller. The PL061 supports 8 bits with interrupt control.
Click to view the PL061 TRM.
PL080 is a synthesizable DMA controller supporting one AHB master interface and eight DMA channels.
Click to view the PL080 TRM.
PL081 is a synthesizable DMA controller supporting one AHB master interface and two DMA channels.
Click to view the PL081 TRM.
PL111 is a synthesizable color LCD controller supporting an AHB master and slave interface and driving TFT and STN, single and dual panel displays.
Click to view the PL111 TRM.
PL192 is an advanced vectored interrupt controller supporting up to 32 vectored interrupts with programmable priority level and masking.
Click to view the PL192 TRM.
PL320 is an Inter-processor communications module for servicing interrupts. It pre-dates the GIC architecture.
Click to view the PL320 TRM.
The Direct Memory Access (DMA) controller enables the movement of blocks of data from peripheral to memory, memory to peripheral, or memory to memory without burdening the processor.DMA-330 TRM
AMBA Level 2 Cache Controller designs boost the performance of AMBA AHB and AXI processors while reducing overall traffic to system memory, and therefore reducing the energy consumption of the SoC.L2C-310 TRM
TrustZone controllers are secure system IP blocks that support the Arm TrustZone system-wide approach to security for preventing access by malicious software to selected memory regions and peripherals such as screens and keypads.TZC-400 TRM