System Memory Management Units

The Arm System Memory Management Units

About System Memory Management Units

A system memory management unit (SMMU) is responsible for all aspects of memory management, including caching and memory virtualization. It gives a common view of memory to all SoC components. It enforces memory protection and access schematic while extending memory virtualization services that match those provided by the main application processor to ensure consistent security across the SoC. The SMMU is designed for use in a virtualized system where multiple guest operating systems are managed by a hypervisor. 

CoreLink System Memory Management Units

The System Memory Management Unit family

MMU-500

CoreLink MMU-500 Memory Management Unit

Accelerated stage 1 and stage 2 address translation for maximum flexibility.

The CoreLink MMU-500 is compatible with the Armv8-A enabled Cortex-A72 and Cortex-A53 processors, and is backwards compatible with the Arm Cortex-A15 and Arm Cortex-A7 processors. It offers nested stage 1 and stage 2 accelerated address translation with multiple distributed translation buffers controlled from a single control unit. It is compatible with a wide range of bus master types and capabilities. offering maximum flexibility in implementing efficient SoC designs that need to support virtualized applications.

MMU-401

Accelerated stage 2 address translation to reduce hypervisor overhead.

The CoreLink MMU-401 is compatible with the Arm Cortex-A15 and Cortex-A7 processors and offers stage 2 accelerated address translation for bus masters that already implement MMU functionality for stage 1 translation, such as the Mali-400 Graphics Processor, thereby reducing the hypervisor overhead in managing complex bus master interactions.

 

Enterprise server system example

Highlights

MMU-500 Features

  • Builds on top of MMU-400 features by implementing SMMUv2 architecture adding support for Armv8 CPUs
  • Supports Stage 1, Stage 2, and Stage1 followed by Stage 2 address translation for up to 128 active device contexts
  • Implements a distributed Translation Buffer Unit (TBU) micro-architecture with direct point-to-point connections between each TBU and the centralized Translation Control Unit (TCU) for Page Table Walks (PTWs)
  • Supports up to 128 entries per TLB which is further backed by TCU cache up to 2K entries

MMU-401 Features

  • Supports SMMUv1 architecture for Armv7 CPUs and Arm v8 for 64KB page sizes
  • Performs stage2 translation only for hypervisor support
  • Implements a single TBU micro-architecture with connection to a single TCU for page table walks

    MMU-500 Characteristics

    The MMU-500 supports the translation formats of Armv7 and Armv8 architectures and performs Stage 1, Stage 2, or Stage 1 followed by Stage 2 translations for all page sizes except 16KB page granule for Armv8. The MMU-500 is implemented as a distributed design with one or more TBUs communicating to a single centralized TCU that performs PTWs to memory. Each TBU can be located in its own clock and power domain making it easy to co-locate the TBU with the peripheral requiring translation. Each TBU communicates to the TCU over an point-to-point stream interface and with bus masters over ACE-Lite. The TCU has an AXI4 slave interface for configuration. 

    Important Documentation

    • MMU-500 Technical Reference Manual

      For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

      MMU-500 TRM
    • MMU-401 Technical Reference Manual

      For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

      MMU-401 TRM
    • SMMUv2 Architecture Spec

      Builds on top of SMMUv1 specification to add support for Armv8 architecture.


      SMMUv2 Spec