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Appendix B. Revisions

This appendix describes the technical changes between released issues of this book.

Table B.1. Issue A
ChangeLocationAffects
No changes, first release.--

Table B.2. Differences between Issue A and Issue B
ChangeLocationAffects
Information added on TBU queue depth support.

Chapter 1 Introduction.

Chapter 2 Functional description.

r1p0.
Information added on 128 contexts support.Chapter 1 Introduction.r1p0.
Information added on support for configuring TCU core to run at half the clock speed compared to TCU external interfaces.

Chapter 1 Introduction.

Chapter 2 Functional description.

r1p0.
Modified page size values for S1 and S2 translation.Chapter 3 Programmers model.All revisions.
Information added on Global address space 1. Chapter 3 Programmers model.All revisions.
Added the dftmcphold signal to Table A.20.Appendix A Signal descriptions.All revisions.
Information added on Peripheral and component identification registers summary. Chapter 3 Programmers modelAll revisions
Information added on TCU and TBU interfaces.

Chapter 1 Introduction.

Chapter 2 Functional description.

All revisions.
Corrected the clock and power domains in Figure 2.4.Chapter 2 Functional description.All revisions.
Information added on TBU barrier support.Chapter 2 Functional description.All revisions.
Added SMMU_TBU_PWR_STATUS register to Integration registers.Chapter 3 Programmers model.All revisions.

Table B.3. Differences between issue B and issue C
ChangeLocationAffects

Information added on the following:

  • Support for 256 outstanding transactions for each TBU master interface.

  • Support for priority elevation as part of QoS scheme.

Chapter 1 Introduction.r2p0.
Information added on the dftmchold signal in Test features.Chapter 1 Introduction.All revisions.
Information added on Programming interface.Chapter 2 Functional description.All revisions.
Information added on Low-power interface for clock gating and power control.Chapter 2 Functional description.All revisions.

Added StreamID configuration information on the following sections:

Chapter 2 Functional description.

Chapter 3 Programmers model.

Appendix A Signal descriptions.

r2p0.
Added information on AXI3 and AXI4 support.Chapter 2 Functional description.All revisions.
Added illustrations on StreamID.Chapter 2 Functional description.All revisions.
Added information on Modes of operation and execution.Chapter 3 Programmers model.All revisions.
Added new registers in Table 3.2.
Added information on Performance monitoring.
Added new register bit in Auxiliary Configuration registers .
Added usage constraint for Auxiliary Control registers.
Updated information on Peripheral and component identification registers summary.
Updated information on Peripheral Identification register 2.
Updated information on Peripheral Identification register 4.

Updated information on the following sections:

Appendix A Signal descriptions.All revisions.

Table B.4. Differences between Issue C and Issue D
ChangeLocationAffects
Added a new signal to Figure 1.2.Chapter 1 Introduction.r2p1.
Added information on AXI3 and AXI4 support.Chapter 2 Functional description.r2p1.
Added new register bit in Auxiliary Configuration registers .Chapter 3 Programmers model.r2p1.
Added a new signal information to Tie-off signals.Appendix A Signal descriptions.r2p1.

Table B.5. Differences between Issue D and Issue E
ChangeLocationAffects
Changed the value of SMMU_IDR7.MINOR [3:0] from 0x1 to 0x2 in Table 3.1.Chapter 3 Programmers model.r2p2.

Table B.6. Differences between Issue E and Issue F
ChangeLocationAffects
Clarified shared configuration description that accompanies Figure 2.4.Low-power interface for clock gating and power control.All revisions.
Added note to clarify that MMU-500 does not support configuration errors.Operation.All revisions.
Clarified statement about memory attribute normalization.AXI3 and AXI4 support.All revisions.
Added information about error handling.Modes of operation and execution.All revisions.
Modified SMMU_IDR7.MINOR value.Table 3.1.r2p4.
Modified SMMU_PMCEID0.EVENT reset values.Table 3.2.All revisions.
Modified SMMU_PIDR3.RevAnd reset value.Table 3.34.All revisions.
Clarified WDW and WSW footnotes.Table A.6.All revisions.
Clarified description of cfg_cttw bit.Table A.20.All revisions.

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