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List of terms

A32
The instruction set used by an ARMv8 processor that is in AArch32 execution state. A32 is a fixed-width instruction set that uses 32-bit instruction encoding. It is compatible with the ARMv7 ARM instruction set.See Also AArch32, T32.
A32 instruction
An instruction executed by a core that is in AArch32 Execution state and A32 Instruction set state. A32 is a fixed-width instruction set that uses 32-bit instruction encodings. Previously, this instruction set was called the Arm instruction set.
A32 state
When a core is in the AArch32 Execution state, if it is in the A32 Instruction set state then it executes A32 instructions.
A64
The instruction set used by an ARMv8 processor that is in AArch64 execution state. A64 is a fixed-width instruction set that uses 32-bit instruction encoding.See Also AArch64, A32, T32.
A64 instruction
The instruction set used by an ARMv8-A core that is in AArch64 Execution state. A64 is a fixed-width instruction set that uses 32-bit instruction encodings.
AAPCS
Defines how registers and the stack are used for subroutine calls.
AArch32
The ARM 32-bit Execution state that uses 32-bit general purpose registers, and a 32-bit program counter (PC), stack pointer (SP), and link register (LR). AArch32 Execution state provides a choice of two instruction sets, A32 and T32. In implementations of versions of the ARM architecture before ARMv8, and in the ARM R and M architecture profiles, execution is always in AArch32 state.
AArch64
The ARM 64-bit Execution state that uses 64-bit general purpose registers, and a 64-bit program counter (PC), stack pointer (SP), and exception link registers (ELR). AArch64 Execution state provides a single instruction set, A64. AArch64 state is supported only in the ARMv8-A architecture profile.
ABI
A collection of specifications, some open and some specific to the Arm architecture, that regulate the inter-operation of binary code in a range of execution environments for Arm processors. The base standard specifies those aspects of code generation that must conform to a standard that supports inter-operation. It is aimed at authors and vendors of C and C++ compilers, linkers, and runtime libraries.
abort
An abort occurs when an illegal memory access causes an exception. An abort can be generated by the hardware that manages memory accesses, or by the external memory system. The hardware that generates the abort might be a Memory Management Unit (MMU) or a Memory Protection Unit (MPU).
abort model
Describes the changes to the core state when a Data abort exception occurs. Different abort models behave differently with regard to load and store instructions that specify base register writeback.
ACE
The AXI Coherency Extensions (ACE) provide additional channels and signaling to an AXI interface to support system level cache coherency.
ACE interface
An AMBA AXI4 interface that includes full support for the ACE protocol. An ACE interface adds: *Signals to some of the AXI4 channels. *Channels to the AXI4 interface.
ACE protocol
The AXI Coherency Extensions protocol, that adds signals to an AMBA AXI4 interface, to support managing the coherency of a distributed memory system.
ACE-Lite interface
Use AMBA ACE on first use. After that, use ACE.
adaptive clocking
A technique where the debug interface hardware sends out a clock signal and then waits for the returned clock before generating the next clock pulse. This technique enables the run control unit in the debug hardware to adapt to differing signal drive capabilities and differing cable lengths.
addressing mode
A method of generating the memory address that a load or store instruction uses.The addressing modes mechanism can generate values for data-processing instructions to use as operands.
Advanced eXtensible Interface
An AMBA bus protocol that supports:separate phases for address or control and data unaligned data transfers using byte strobes burst-based transactions with only start address issued separate read and write data channels issuing multiple outstanding addresses out-of-order transaction completionaddition of register stages to provide timing closure.The AXI protocol includes optional signaling extensions for low-power operation.See Also AXI Coherency Extensions (ACE).
Advanced High-performance Bus
An AMBA bus protocol supporting pipelined operation, with the address and data phases occurring during different clock periods. This means the address phase of a transfer can occur during the data phase of the previous transfer. AHB provides a subset of the functionality of the AMBA AXI protocol. See Also Advanced Microcontroller Bus Architecture (AMBA) and AHB-Lite.
Advanced Microcontroller Bus Architecture
The AMBA family of protocol specifications is the ARM open standard for on-chip buses. AMBA provides solutions for the interconnection and management of the functional blocks that make up a System-on-Chip (SoC). Applications include the development of embedded systems with one or more processors or signal processors and multiple peripherals.
Advanced Peripheral Bus
An AMBA bus protocol for ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. Using APB to connect to the main system bus through a system-to-peripheral bus bridge can help reduce system power consumption.
Advanced SIMD
A feature of the ARM architecture that provides Single Instruction Multiple Data (SIMD) operations on a dedicated bank of registers. If an implementation also supports scalar floating-point instructions, the floating-point and Advanced SIMD instructions use a common register bank. ARM NEON technology provides the Advanced SIMD instructions, and therefore these are sometimes called the NEON instructions.
Advanced Trace Bus
An AMBA bus protocol for trace data. A trace device can use an ATB to share CoreSight capture resources. Use AMBA ATB on first use, and ATB thereafter.
AEL
A version of embedded Linux OS ported to the Arm architecture.
AHB
An AMBA bus protocol supporting pipelined operation, with the address and data phases occurring during different clock periods. This means the address phase of a transfer can occur during the data phase of the previous transfer. AHB provides a subset of the functionality of the AMBA AXI protocol. See Also Advanced Microcontroller Bus Architecture (AMBA) and AHB-Lite.
AHB Access Port
An optional component of the DAP that provides an AHB interface to a SoC.CoreSight supports access to a system bus infrastructure using the AHB Access Port (AHB-AP) in the Debug Access Port (DAP). The AHB-AP provides an AHB master port for direct access to system memory. Other bus protocols can use AHB bridges to map transactions. For example, you can use AHB to AXI bridges to provide AHB access to an AXI bus matrix.See Also Debug Access Port (DAP).
AHB Trace Macrocell
A trace source that makes bus information visible. This information cannot be inferred from the processor using just a trace macrocell. HTM trace can provide: An understanding of multi-layer bus utilization.Software debug. For example, visibility of access to memory areas and data accesses.Bus event detection for trace trigger or filters, and for bus profiling.See Also Advanced High-performance Bus (AHB).
AHB-AP
An optional component of the DAP that provides an AHB interface to a SoC.CoreSight supports access to a system bus infrastructure using the AHB Access Port (AHB-AP) in the Debug Access Port (DAP). The AHB-AP provides an AHB master port for direct access to system memory. Other bus protocols can use AHB bridges to map transactions. For example, you can use AHB to AXI bridges to provide AHB access to an AXI bus matrix.See Also Debug Access Port (DAP).
AHB-Lite
A subset of the full AMBA AHB protocol specification. It provides all of the basic functions required by the majority of AMBA AHB slave and master designs, particularly when used with a multi-layer AMBA interconnect.
APB
An AMBA bus protocol for ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. Using APB to connect to the main system bus through a system-to-peripheral bus bridge can help reduce system power consumption.
APB Access Port
An optional component of the Debug Access Point (DAP) that provides an APB interface to a SoC, usually to its main functional buses.
APB-AP
An optional component of the Debug Access Point (DAP) that provides an APB interface to a SoC, usually to its main functional buses.
Application Binary Interface for the Arm Architecture
A collection of specifications, some open and some specific to the Arm architecture, that regulate the inter-operation of binary code in a range of execution environments for Arm processors. The base standard specifies those aspects of code generation that must conform to a standard that supports inter-operation. It is aimed at authors and vendors of C and C++ compilers, linkers, and runtime libraries.
Application Processor Status Register
In AArch32 User mode, a restricted form of the CPSR.
APSR
In AArch32 User mode, a restricted form of the CPSR.
Arm Compiler for DS-5
Arm Compiler for DS-5 is a suite of tools, together with supporting documentation and examples, that you can use to write and build applications for the Arm family of processors. Arm Compiler for DS-5 supersedes RealView Compilation Tools.See Also armar, armasm, armcc, fromelf.
Arm Debug Interface
The ADI connects a debugger to a device. The ADI is used to access memory-mapped components in a system, such as processors and CoreSight components. The ADI protocol defines the physical wire protocols permitted, and the logical programmers model.
Arm Embedded Linux
A version of embedded Linux OS ported to the Arm architecture.
Arm instruction
An instruction executed by a core that is in AArch32 Execution state and A32 Instruction set state. A32 is a fixed-width instruction set that uses 32-bit instruction encodings. Previously, this instruction set was called the Arm instruction set.
Arm profiler
A plug-in to the ARM Workbench Integrated Development Environment that provides non-intrusive analysis of embedded software over time, on targets running at frequencies which are typically as high as 250MHz. Targets can be Real-Time System Models (RTSMs) and hardware targets.See Also RealView Development Suite (RVDS).
Arm state
When a core is in the AArch32 Execution state, if it is in the A32 Instruction set state then it executes A32 instructions.
Arm TrustZone technology
The hardware and software that enable the integration of enhanced security features throughout a SoC. In Armv6K and Armv7, the Security Extensions implement the TrustZone hardware. In Armv8, EL3 incorporates the TrustZone hardware.
Arm Workbench IDE
Arm Workbench IDE is based around the Eclipse IDE, and provides additional features to support the Arm development tools provided in RVDS.See Also RealView Development Suite (RVDS).
armar
The ARM librarian which enables you to create libraries of files, such as object files.See Also Development Studio 5 (DS-5) and RealView Compilation Tools (RVCT).
armasm
The ARM assembler. This converts ARM assembly language into machine code.See Also Development Studio 5 (DS-5) and RealView Compilation Tools (RVCT).
armcc
The ARM compiler for C and C++ code.See Also Development Studio 5 (DS-5) and RealView Compilation Tools (RVCT).
ArtiGrid
A power routing scheme, also referred to as Over The Cell.See Also Over The Cell (OTC).
ATB
An AMBA bus protocol for trace data. A trace device can use an ATB to share CoreSight capture resources. Use AMBA ATB on first use, and ATB thereafter.
ATB bridge
A synchronous ATB bridge provides a register slice that meets timing requirements by adding a pipeline stage. It provides a unidirectional link between two synchronous ATB domains. An asynchronous ATB bridge provides a unidirectional link between two ATB domains with asynchronous clocks. This means it connects components in different clock domains.
atomicity
Describes actions that appear to happen as a single operation. In the ARM architecture, atomicity refers to either single-copy atomicity or multi-copy atomicity. The ARM Architecture Reference Manuals define these forms of atomicity.
ATPG
Automated Test Pattern Generation: The process of using a specialized software tool to automatically generate manufacturing test vectors for an ASIC design.
authentication asynchronous bridge
Transfers authentication signals between two asynchronous clock domains.
authentication synchronous bridge
Transfers authentication signals between two synchronous clock domains.
Automatic Test Pattern Generation
Automated Test Pattern Generation: The process of using a specialized software tool to automatically generate manufacturing test vectors for an ASIC design.
AWIDE
Arm Workbench IDE is based around the Eclipse IDE, and provides additional features to support the Arm development tools provided in RVDS.See Also RealView Development Suite (RVDS).
AXI
An AMBA bus protocol that supports:separate phases for address or control and data unaligned data transfers using byte strobes burst-based transactions with only start address issued separate read and write data channels issuing multiple outstanding addresses out-of-order transaction completionaddition of register stages to provide timing closure.The AXI protocol includes optional signaling extensions for low-power operation.See Also AXI Coherency Extensions (ACE).
AXI Coherency Extensions
The AXI Coherency Extensions (ACE) provide additional channels and signaling to an AXI interface to support system level cache coherency.
AXI low-power interface
Deprecated variant of AXI low-power interface
back-annotation
The process of applying timing characteristics from the implementation process onto a model.
banked register
A register that has multiple instances. A property of the state of the device determines which instance is in use. For example, the Security state might determine which instance is in use.
Base Platform Application Binary Interface
The base standard for the interface between executable files, such as dynamic shared objects and DLLs, and the systems that execute them.
base porting layer
A platform-dependent base driver software component that communicates with the Mali GPU. For example, the base porting layer controls the Mali GPU registers. You implement, or port, the base porting layer onto different target platforms.
base register
A register specified by a load or store instruction that is used as the base value for the address calculation for the instruction. Depending on the instruction, an offset can be added to or subtracted from the base register value to form the address that is used for the memory access.
Base Standard Application Binary Interface
A collection of specifications, some open and some specific to the Arm architecture, that regulate the inter-operation of binary code in a range of execution environments for Arm processors. The base standard specifies those aspects of code generation that must conform to a standard that supports inter-operation. It is aimed at authors and vendors of C and C++ compilers, linkers, and runtime libraries.
BCD file
In the context of RealView Debugger, a BCD file enables you to define the memory map and memory-mapped registers for a target development board or processor. ARM provides various BCD files with RVDS for ARM development boards.See Also Board file and Debug configuration.
big-endian
In the context of the ARM architecture, big-endian is defined as the memory organization in which the least significant byte of a word is at a higher address than the most significant byte, for example: *A byte or halfword at a word-aligned address is the most significant byte or halfword in the word at that address. *A byte at a halfword-aligned address is the most significant byte in the halfword at that address.
Board and Chip Definition file
In the context of RealView Debugger, a BCD file enables you to define the memory map and memory-mapped registers for a target development board or processor. ARM provides various BCD files with RVDS for ARM development boards.See Also Board file and Debug configuration.
board file
A debugger uses this term to refer to the top-level configuration file, normally called rvdebug.brd, that references one or more other configuration files. A board file contains:the Debug Configuration (connection-level) settingsreferences to the Debug Interface configuration file that identifies the targets on the development platformreferences to any Board and Chip Definition (BCD) files assigned to a Debug Configuration.See Also Board and Chip Definition (BCD) file and Debug configuration.
bounce
In an ARMv7 floating-point implementation that includes a VFP subarchitecture, a mechanism for handling floating point exceptions and instructions that are not supported by the hardware. A bounce generates an Undefined Instruction exception, and the exception handler can call support code to respond to the bounce.
boundary scan chain
A boundary scan chain is made up of serially-connected devices that implement boundary scan technology using a standard JTAG TAP interface. Each device contains at least one TAP controller containing shift registers that form the chain, connected between TDI and TDO, through which test data is shifted. A processor can contain several shift registers, enabling you to access selected parts of the device.
BPABI
The base standard for the interface between executable files, such as dynamic shared objects and DLLs, and the systems that execute them.
branch folding
A technique where, on the prediction of a branch, the target instructions are completely removed from the instruction stream presented to the execution pipeline. Branch folding can significantly improve the performance of branches, and take the CPI for branches below one.
branch phantom
Branch target instructions speculatively executed, in parallel with the main instruction stream, as a result of branch folding.
branch prediction
The selection of a future execution path for instruction fetch. For example, after a branch instruction, the processor can choose to speculatively fetch either the instruction following the branch or the instruction at the branch target.See Also Prefetching.
breakpoint
A debug event triggered by the execution of a particular instruction. It is specified by one or both of the address of the instruction and the state of the processor when the instruction is executed.See Also Watchpoint.
BSABI
A collection of specifications, some open and some specific to the Arm architecture, that regulate the inter-operation of binary code in a range of execution environments for Arm processors. The base standard specifies those aspects of code generation that must conform to a standard that supports inter-operation. It is aimed at authors and vendors of C and C++ compilers, linkers, and runtime libraries.
byte lane strobe
A signal that determines which byte lanes are active, or valid, in a data transfer. Each bit of this signal corresponds to eight bits of the data bus.
byte swizzling
Re-arranging the order of bytes in a word or halfword.
byte-invariant
In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access.The ARM architecture supports byte-invariant systems in ARMv6 and later versions.See Also Word-invariant.
cacheable
A data storage method in which, if a memory location to be written is not in cache memory, a cache line is allocated for the memory. The value of that memory is then loaded into the cache from main memory, and the new value for the location is written to cache.
CADI
The debug control and inspection API to a fast model.
Canonical Frame Address
In Debug With Arbitrary Record Format (DWARF), this is an address on the stack specifying where the call frame of an interrupted function is located.
captive thread
Captive threads are all threads that can be brought under the control of RVDS. Special threads, called non-captive threads, are essential to the operation of Running System Debug (RSD) and so are not under debugger control.See Also Running System Debug (RSD).
cast out
A cache line, selected to be discarded to make room for a replacement cache line that is required because of a cache miss. How the victim is selected for eviction is processor-specific. A victim is also known as a cast out.
CFA
In Debug With Arbitrary Record Format (DWARF), this is an address on the stack specifying where the call frame of an interrupted function is located.
chained breakpoint
In the context of an ARM debugger, a complex breakpoint that comprises multiple hardware breakpoint units.See Also Breakpoint unit and Conditional breakpoint.
chained tracepoint
In the context of an ARM debugger, a complex tracepoint that comprises multiple tracepoint units.See Also Tracepoint unit and Tracepoint.
channel interface
In an ECT device, channel interface is one of the interfaces on CTI.
characterized
Designates a cell that includes timing data.
clean
A cache line that has not been modified while it is in the cache is said to be clean. To clean a cache is to write dirty cache entries to main memory.
clock gating
Gating a clock signal for a macrocell or functional block with a control signal and using the modified clock that results to control the operating state of the macrocell or block.
Clocks Per Instruction
The average number of clock cycles per instruction for a program or program fragment. It is the multiplicative inverse of instructions per cycle. You can use this value to compare the performance of different processors that implement the same instruction set. The lower the value, the better the performance.
cluster
A cluster is a collection of cores, particularly having a shared cache. Cluster is preferred to the terms "multiprocessor" and "multi-core".
CMM
In the context of an ARM debugger, a scripting language provided for compatibility with other debuggers.If you are writing new scripts, ARM recommends that you use the GNU Debugger (GDB) scripting commands because these offer more functionality in the ARM Debuggers.
coherence order
Data accesses from a set of observers to a byte in memory are coherent if accesses to that byte by the members of the set of observers are consistent with there being a single total order of all writes to that byte in memory by all members of the set of observers. This single total order of all writes to that byte is the coherence order for that byte.
coherent
Data accesses from a set of observers to a byte in memory are coherent if accesses to that byte by the members of the set of observers are consistent with there being a single total order of all writes to that byte in memory by all members of the set of observers. This single total order of all writes to that byte is the coherence order for that byte.
Cold reset
A Cold reset has the same effect as starting the processor by turning the power on. This clears main memory and many internal settings. Some program failures can lock up the core and require a Cold reset to restart the system.
Communications channel
The hardware used for communicating between the software running on the processor, and an external host, using the debug interface. When this communication is for debug purposes, it is called the Debug Communications Channel (DCC).See Also Debug Communications Channel (DCC).
Condensed Reference Format
An ARM proprietary file format for specifying test vectors. Typically, ARM supplies a script to convert CRF format to Verilog Reference Format (VRF).
condition code check
The process of determining whether a conditional instruction executes normally or is treated as a NOP. For an instruction that includes a condition code field, that field is compared with the condition flags to determine whether the instruction is executed normally. For a T32 instruction in an IT block, the value of the ITSTATE register determines whether the instruction is executed normally.
condition code field
A four-bit field in an ARM instruction that specifies the condition under which the instruction executes.See Also Conditional execution and Condition flags.
condition flags
Condition flags is the agreed term. The condition flags are the N, Z, C, and V bits of PSTATE or of a Program Status Register (PSR).
conditional breakpoint
A breakpoint that has one or more condition qualifiers assigned. The breakpoint is activated when all assigned conditions are met, and either stops or continues execution depending on the action qualifiers that are assigned. The condition normally references the values of program variables that are in scope at the breakpoint location.See Also Chained breakpoint and Software breakpoint.
conditional execution
When a conditional instruction starts executing, if the condition code check returns TRUE, the instruction executes normally. Otherwise, it is treated as NOP.
CONSTRAINED UNPREDICTABLE
Where an instruction can result in unpredictable behavior, the ARM architecture can specify a narrow range of permitted behaviors. This range is the range of CONSTRAINED UNPREDICTABLE behavior. All implementations that are compliant with the architecture must follow the CONSTRAINED UNPREDICTABLE behavior. However, software must not rely on any CONSTRAINED UNPREDICTABLE behavior. When CONSTRAINED UNPREDICTABLE appears in body text, it is always in SMALL CAPITALS.
context switch
The saving and restoring of computational state when switching between different threads or processes. Context switch describes any situation where the context is switched by an operating system and might or might not include changes to the address space.
Context synchronization event
Depending on the context, using 'Context synchronization event' or 'Context synchronization instruction'. One of: • Performing an ISB operation. An ISB operation is performed when an ISB instruction is executed and does not fail its condition code check. • Taking an exception. • Returning from an exception. • Exit from Debug state. • Executing a DCPS instruction. • Executing a DRPS instruction. The architecture requires a Context synchronization event to guarantee visibility of any change to a System register.
coprocessor
A processor, or conceptual processor, that supplements the main processor to carry out additional functions. In AArch32 Execution state, the ARM architecture defines an interface to up to 16 coprocessors, CP0-CP15. In ARMv8, AArch32 state supports only conceptual coprocessors CP10, CP11, CP14, and CP15. In previous versions of the architecture, coprocessors CP0-CP7 are available for implementation defined features, and coprocessors CP8-CP15 are reserved for use by ARM. In all architecture versions for the A and R architecture profiles, in AArch32 state: CP15 instructions access the System registers. Some documentation describes this set of registers as the System Control Coprocessor. CP14 instructions access System registers for debug, trace, and execution environment features. The CP10 and CP11 instruction space is for floating-point and Advanced SIMD instructions if supported, including the instructions for accessing the floating-point and Advanced SIMD System registers.
core
Core is used to describe a single processing unit. In the application processor area we can further define core as something that has exclusive use of its own program counter (PC). Never use CPU to refer to a core or PE. Do not try to introduce local definitions of CPU to get round this rule.
core module
In the context of an ARM Integrator development board, an add-on development board that contains an ARM processor and local memory. Core modules can run standalone, or can be stacked onto Integrator development boards.See Also Integrator.
core register
Use 'source general-purpose register'. Processing registers used in AArch32 Execution state, comprising: 13 general-purpose registers, R0 to R12, that software uses for all data processing when using the base instruction set instructions. SP, the Stack Pointer, that can also be referred to as R13. LR, the Link Register, that can also be referred to as R14. PC, the Program Counter, that can also be referred to as R15. In some situations, software can use SP, LR, and PC for processing. The instruction descriptions include any constraints on the use of SP, LR, and PC.
Core reset
Also known as a core reset. Initializes most of the processor functionality, excluding the debug controller and debug logic. This type of reset is useful if you are using the debugging features of a processor.See also Cold reset.
CoreSight ECT
A modular system that supports the interaction and synchronization of multiple triggering events with an SoC. It comprises:Cross Trigger Interface (CTI)Cross Trigger Matrix (CTM).
CoreSight ETB
A Logic block that extends the information capture functionality of a trace macrocell.
CoreSight ETM
A hardware macrocell that, when connected to a processor, outputs trace information on a trace port. The ETM provides processor driven trace through a trace port compliant to the ATB protocol. An ETM always supports instruction trace, and might support data trace.
Cortex Microcontroller Software Interface Standard
(CMSIS) Defines a common way to access peripheral regiseters or define excpetion vectors. CMSIS is the name of the core exception vectors, and a device-independent interface for RTOS kernels, including a debug channel.
CPI
The average number of clock cycles per instruction for a program or program fragment. It is the multiplicative inverse of instructions per cycle. You can use this value to compare the performance of different processors that implement the same instruction set. The lower the value, the better the performance.
CPSR
In AArch32 state, the register that holds the current program status.
CRF
An ARM proprietary file format for specifying test vectors. Typically, ARM supplies a script to convert CRF format to Verilog Reference Format (VRF).
Cross Trigger Interface
Part of an Embedded Cross Trigger (ECT) device. In an ECT, the CTI provides the interface between a processor or ETM and the CTM.
Cross Trigger Matrix
In an ECT device, the CTM combines the trigger requests generated by CTIs and broadcasts them to all CTIs as channel triggers.
cross-path blocking
Cross-path blocking occurs when a divergent node has congestion on one of its output nodes which blocks bus traffic to its other output nodes.
CTI
Part of an Embedded Cross Trigger (ECT) device. In an ECT, the CTI provides the interface between a processor or ETM and the CTM.
CTM
In an ECT device, the CTM combines the trigger requests generated by CTIs and broadcasts them to all CTIs as channel triggers.
Current Program Status Register
In AArch32 state, the register that holds the current program status.
Cycles Per Instruction
The average number of clock cycles per instruction for a program or program fragment. It is the multiplicative inverse of instructions per cycle. You can use this value to compare the performance of different processors that implement the same instruction set. The lower the value, the better the performance.
DA
Debug Agent: In RealView Debugger, the debug agent provides target-side support for Running System Debug (RSD). The debug agent can be a thread or be built into the RTOS. The debug agent and RealView Debugger communicate with each other using the DCC. This passes data between the debugger and the target using a hardware debug interface, without stopping the program or entering debug state.See Also Running System Debug (RSD) and Debug Communications Channel (DCC). -or- Design Assurance, or Design Automation - Design Assurance = Validation; Design Automation = in-house EDA automation infrastructure
DAP
A block that acts as a master on a system bus and provides access to the bus from an external debugger.
Data Abort
An indication to the core of an attempted data access that is not permitted. The Data Abort might be generated by access permission checks performed by the memory system on the core, or might be signaled by the memory system.
data breakpoint
A hardware breakpoint that activates when an access to a specified location meets a set of specified conditions. The conditions can include a check for a specific data value being accessed at the given location.See Also Chained breakpoint and Conditional breakpoint.
Data Timing Module
In the context of physical IP, a data timing module that synchronizes incoming and outgoing data. The DTM is a component of PHY to include I/Os and PLL.
data-active write transaction
A transaction that has completed the address transfer or leading write data transfer, but has not completed all of its data transfers.
DBGTAP
A debug control and data interface based on IEEE 1149.1 JTAG Test Access Port (TAP). The interface has four or five signals.
DCC
A channel that carries data between a debugger and debug logic in the target processor. It can do this without stopping the program flow or causing entry to Debug state, but can also be used when the target is in Debug state. The DCC is part of the debug register interface of the target.
Debug Access Port
A block that acts as a master on a system bus and provides access to the bus from an external debugger.
debug agent
Debug Agent: In RealView Debugger, the debug agent provides target-side support for Running System Debug (RSD). The debug agent can be a thread or be built into the RTOS. The debug agent and RealView Debugger communicate with each other using the DCC. This passes data between the debugger and the target using a hardware debug interface, without stopping the program or entering debug state.See Also Running System Debug (RSD) and Debug Communications Channel (DCC). -or- Design Assurance, or Design Automation - Design Assurance = Validation; Design Automation = in-house EDA automation infrastructure
Debug Communications Channel
A channel that carries data between a debugger and debug logic in the target processor. It can do this without stopping the program flow or causing entry to Debug state, but can also be used when the target is in Debug state. The DCC is part of the debug register interface of the target.
debug configuration
In the context of an ARM debugger, a debug configuration defines a debugging environment for the development platform that is accessed through a particular Debug Interface. Multiple debug configurations can be created for a debug interface, each providing a separate debugging environment to different development platforms, or different debugging environments to the same development platform.All debug configurations are stored in the main debugger board file. Each configuration might reference one or more BCD files.See Also Board file and Target.
debug illusion
The view of the software being debugged that a debugger presents to its user. The features of the debug illusion include:Mapping between assembler code and source code, including displaying assembler and source code simultaneously if required.Support for source-level stepping and breakpoints.Visibility of the source-level function call stack, even when called functions are generated inline.Display of variable values and structure field values, even when these values migrate between various locations. This includes displaying registers and the stack.
debug interface
In the context of RealView Debugger, the Debug interface identifies the targets on your development platform, and provides the mechanism that enables RealView Debugger to communicate with those targets. The Debug interface corresponds directly to a piece of hardware or a software simulator.See Also Debug configuration and Target.
Debug Test Access Port
A debug control and data interface based on IEEE 1149.1 JTAG Test Access Port (TAP). The interface has four or five signals.
Default NaN mode
In floating-point operation, a mode in which all operations that result in a NaN return the default NaN, regardless of the cause of the NaN result. This mode is compliant with the IEEE 754 standard but implies that all information contained in any input NaNs to an operation is lost.See Also NaN.
denormalized value
The IEEE 754-2008 standard term for a floating-point operand with a zero exponent and a nonzero fraction field. ARM documentation describes these operands as denormal or denormalized, as defined by the IEEE 754-1985 standard. Note ARM floating-point implementations comply with the IEEE 754 requirement that denormalized operands are generated and manipulated with the same precision as normal operands. Plus or minus 0 have zero exponent fields, but are not denormals because there is no loss of accuracy.
Design Simulation Model
A functional simulation model of the device derived from the Register Transfer Level (RTL) but that does not reveal its internal structure. The DSM does not model any features added during synthesis such as internal scan chains.
Development Studio 5
The suite of software development tools, together with supporting documentation and examples, that enable you to write and debug applications for the ARM family of processors. DS-5 supersedes RealView Development Suite.See Also RealView Development Suite (RVDS).
device
In the context of an ARM debugger, a component on a target. The device contains the application that you want to debug.
Device Validation Suite
Use this set of tests to check the functionality of a device against that defined in the Technical Reference Manual.
Direct-mapped cache
A one-way set-associative cache. Each cache set consists of a single cache line, so cache look-up selects and checks a single cache line.
dirty
A line in a Write-Back cache that has been modified while it is in the cache. Typically, a cache line is marked as dirty by setting the dirty bit to 1.
DNM
A value that must not be altered by software. DNM fields read as UNKNOWN values, and must only be written with the value read from the same field on the same processor.
Do-Not-Modify
A value that must not be altered by software. DNM fields read as UNKNOWN values, and must only be written with the value read from the same field on the same processor.
doubleword
A 64-bit data item. Doublewords are normally at least word-aligned in ARM systems. Must not be hyphenated. Use doubleword.
doubleword-aligned
Hyphenate doubleword-aligned. A data item having a memory address that is divisible by eight.
draw mode
In the context of graphics processing, one of the different ways to specify the primitives to draw. These different ways are called draw modes. The primitives can be specified individually or as a connected strip or fan. They can also be either:non-indexed, meaning that vertices are passed in a vertex array and processed in orderindexed, meaning that vertices are passed as indices into a vertex array.
DS-5
The suite of software development tools, together with supporting documentation and examples, that enable you to write and debug applications for the ARM family of processors. DS-5 supersedes RealView Development Suite.See Also RealView Development Suite (RVDS).
DS-5 Debugger
An ARM software development tool that enables you to make use of a debug agent to examine and control the execution of software running on a debug target. It is fully integrated into Eclipse for DS-5.See Also Eclipse for DS-5.
DSM
A functional simulation model of the device derived from the Register Transfer Level (RTL) but that does not reveal its internal structure. The DSM does not model any features added during synthesis such as internal scan chains.
DTM
In the context of physical IP, a data timing module that synchronizes incoming and outgoing data. The DTM is a component of PHY to include I/Os and PLL.
DVS
Use this set of tests to check the functionality of a device against that defined in the Technical Reference Manual.
Early-Z
A Z-testing scheme that performs the actual Z-test before texturing or fragment shading when it is safe to do so. This increases the performance of the Mali GPU and reduces the required bandwidth.
Eclipse for DS-5
Eclipse for DS-5 is based around the Eclipse IDE, and provides additional features to support the ARM development tools provided in DS-5.See Also Development Studio 5 (DS-5).
ECT
A modular system that supports the interaction and synchronization of multiple triggering events with an SoC. It comprises:Cross Trigger Interface (CTI)Cross Trigger Matrix (CTM).
EGL
A standardized set of functions that communicate between graphics software, such as OpenGL ES or OpenVG drivers, and the platform-specific windowing system that displays the image.
ELR
In AArch64 state, there is a dedicated LR for each implemented Exception level, called the Exception Link Register (ELR) for that Exception level, for example, ELR_EL1. The Exception Link Register holds the exception return address.
embedded assembler
Embedded assembler is assembler code that is included in a C or C++ file, and is separate from other C or C++ functions.
Embedded Cross Trigger
A modular system that supports the interaction and synchronization of multiple triggering events with an SoC. It comprises:Cross Trigger Interface (CTI)Cross Trigger Matrix (CTM).
Embedded Trace Buffer
A Logic block that extends the information capture functionality of a trace macrocell.
Embedded Trace Macrocell
A hardware macrocell that, when connected to a processor, outputs trace information on a trace port. The ETM provides processor driven trace through a trace port compliant to the ATB protocol. An ETM always supports instruction trace, and might support data trace.
EmbeddedICE logic
An on-chip logic block that provides TAP-based debug support for an ARM processor. It is accessed through the DAP on the ARM processor.
EmbeddedICE-RT
Hardware provided by an ARM processor to aid debugging in real-time.
Embedded-System Graphics Library
A standardized set of functions that communicate between graphics software, such as OpenGL ES or OpenVG drivers, and the platform-specific windowing system that displays the image.
endianity
The scheme that determines the order of the successive bytes of data in a larger data structure when that structure is stored in memory.
endianness
The scheme that determines the order of the successive bytes of data in a larger data structure when that structure is stored in memory.
ESSL
A programming language used to create custom shader programs that can be used in a programmable pipeline, on the Mali GPU. You can also use pre-defined library shaders, written in ESSL.
ESSL compiler
The compiler that translates shaders written in ESSL, into binary code for the shader units in the Mali GPU. There are two versions of the ESSL compiler:the on-target compilerthe offline compiler.
ETB
A Logic block that extends the information capture functionality of a trace macrocell.
ETM
A hardware macrocell that, when connected to a processor, outputs trace information on a trace port. The ETM provides processor driven trace through a trace port compliant to the ATB protocol. An ETM always supports instruction trace, and might support data trace.
ETV
Extended Target Visibility enables RealView Debugger to access features of the underlying target such as, for example, chip-level information provided by the hardware manufacturer or SoC designer.
Event
In the context of an ARM trace macrocell, events can be: *Simple -An observable condition that a trace macrocell can use to control aspects of a trace. *Complex -A boolean combination of simple events that a trace macrocell can use to control aspects of a trace.
event asynchronous bridge
A fixed component that synchronizes events on a single channel from the slave domain to the master domain. In addition, the event acknowledge from the master domain is synchronized and signaled to the slave domain.
exception
A mechanism to handle a fault, error event, or external notification. For example, exceptions handle external interrupts and undefined instructions.
Exception level
Do not use EL when you mean Exception level. Use only Exception level.
Exception Link Register
In AArch64 state, there is a dedicated LR for each implemented Exception level, called the Exception Link Register (ELR) for that Exception level, for example, ELR_EL1. The Exception Link Register holds the exception return address.
exception vector
A fixed address that contains the address of the first instruction of the corresponding exception handler.
exceptional state
In an ARMv7 implementation that includes a VFP subarchitecture, in floating-point operation, if the floating-point hardware detects an exceptional condition, the ARM floating-point implementation sets the FPEXC bit and loads a copy of the exceptional instruction to the FPINST register. When in the exceptional state, the issue of a trigger instruction to the floating-point extension causes a bounce.
execution vehicle
A part of the debug target interface that processes requests from the client tools to the target.See Also Debug interface.
execution view
The address of regions and sections after the image is loaded into memory and started execution.See Also Scatter-loading and Load view.
explicit access
A read from memory, or a write to memory, generated by a load or store instruction executed by the core. Reads and writes generated by hardware translation table accesses are not explicit accesses. For more information, see the appropriate ARM Architecture Reference Manual.
Extended Target Visibility
Extended Target Visibility enables RealView Debugger to access features of the underlying target such as, for example, chip-level information provided by the hardware manufacturer or SoC designer.
eXtensible Verification Component
A model that provides system or device stimulus and monitor responses.See Also XVC Test Scenario Manager.
Fast Context Switch Extension
Before ARMv8, an extension to the ARM architecture that modifies the behavior of the memory system. It enables multiple programs running on the core to use identical address ranges, while ensuring that the addresses they present to the rest of the memory system differ. From ARMv6, ARM deprecates use of the FCSE. The FCSE is optional in ARMv7, and obsolete from the ARMv7 Multiprocessing Extensions.
Fast Model
Simulation in software of Arm SoCs or subsystems, including processors and peripherals.
fault
An abort generated by the memory system, for example by the Memory Management Unit (MMU) or Memory Protection Unit (MPU).
FCSE
Before ARMv8, an extension to the ARM architecture that modifies the behavior of the memory system. It enables multiple programs running on the core to use identical address ranges, while ensuring that the addresses they present to the rest of the memory system differ. From ARMv6, ARM deprecates use of the FCSE. The FCSE is optional in ARMv7, and obsolete from the ARMv7 Multiprocessing Extensions.
FIQ
FIQ interrupt. nFIQ is one of two interrupt signals on many ARM processors. See Also IRQ.
fixed-function pipeline
In the context of graphics processors, a process that uses standard functions to draw graphics on fixed-function graphics processors, such as the Mali-55 GPU. The fixed-function pipeline is a requirement of OpenGL ES 1.1.
Flash Patch and Breakpoint
In an ARM M-profile processor, an FPB can:remap sections of ROM, typically Flash memory, to regions of RAMset breakpoints on code in ROM. It can be used for debug, and to provide a code or data patch to an application that requires field updates to a product ROM.
flat address mapping
A memory system where the physical address for every access is equal to its virtual address.
floating point
Hyphenate floating-point.
floating-point
Hyphenate floating-point.
flush to-zero
In floating-point operation, a mode that optimizes the performance of some floating-point algorithms by replacing the denormalized operands and intermediate results with zeros, without significantly affecting the accuracy of their final results. Using the Flush to Zero mode is a deviation from IEEE 754.
Flush-to-zero mode
In floating-point operation, a special processing mode that optimizes the performance of some floating-point algorithms by replacing the denormalized operands and intermediate results with zeros, without significantly affecting the accuracy of their final results. Capitalize the F.
FPB
In an ARM M-profile processor, an FPB can:remap sections of ROM, typically Flash memory, to regions of RAMset breakpoints on code in ROM. It can be used for debug, and to provide a code or data patch to an application that requires field updates to a product ROM.
fragment
In the context of graphics processors, a fragment consists of all data, such as depth, stencil, texture, and color information, required to generate a pixel in the frame buffer. A pixel usually comprises several fragments.
fragment processor
A programmable processor that performs rendering operations to produce a final image for display. The fragment processor receives completed vertex data from the vertex processor and then runs fragment shader programs.The fragment processor was originally known as a pixel processor.
fragment shader
A program running on the fragment processor that calculates the color and other characteristics of each fragment.
fragment thread creator
In a Mali GPU, a functional block that creates and issues threads to the tri-pipe processing unit pipeline. It is used for all fragment jobs output from the tiler.
frame buffer
A frame buffer (or sometimes framestore) is a portion of RAM containing a bitmap that is driven to a video display from a memory buffer containing a complete frame of data. The information in the memory buffer typically consists of color values for every pixel (point that can be displayed) on the screen.
fromelf
The ARM image conversion utility. This accepts ELF format input files and converts them to a variety of output formats. fromelf can also generate text information about the input image, such as code and data size.See Also RealView Compilation Tools (RVCT).
fully-associative cache
A cache that has only one cache set, that consists of the entire cache. See Also Direct-mapped cache.
general-purpose register
Use 'source general-purpose register'. Processing registers used in AArch32 Execution state, comprising: 13 general-purpose registers, R0 to R12, that software uses for all data processing when using the base instruction set instructions. SP, the Stack Pointer, that can also be referred to as R13. LR, the Link Register, that can also be referred to as R14. PC, the Program Counter, that can also be referred to as R15. In some situations, software can use SP, LR, and PC for processing. The instruction descriptions include any constraints on the use of SP, LR, and PC.
Generic Interrupt Controller
A Generic Interrupt Controller (GIC) is an exclusive block of IP that performs critical tasks of interrupt management, prioritization and routing. GICs are primarily used for boosting processor efficiency and supporting interrupt virtualization. GICs are implemented based on ARM GIC architecture which has evolved from GICv1 to latest version GICv3/v4. ARM has a number of multi-cluster CPU interrupt controllers that provide a range of interrupt management solutions for all types of ARM Cortex processor systems.
generic thread creator
In a Mali GPU, a functional block that creates and issues threads to the tri-pipe processing unit pipeline. It is used for all non-fragment jobs, including vertex shading, geometry shading, and OpenCL jobs.
GIC
A Generic Interrupt Controller (GIC) is an exclusive block of IP that performs critical tasks of interrupt management, prioritization and routing. GICs are primarily used for boosting processor efficiency and supporting interrupt virtualization. GICs are implemented based on ARM GIC architecture which has evolved from GICv1 to latest version GICv3/v4. ARM has a number of multi-cluster CPU interrupt controllers that provide a range of interrupt management solutions for all types of ARM Cortex processor systems.
G-POP
A POP that includes components for an ARM MALI Graphics Processor.See Also POP.
GPR
Used by a debugger to control powerup and powerdown of specific components within a CoreSight system.
GPU
Graphics Processing Unit: A hardware accelerator for graphics systems using OpenGL ES and OpenVG. The Mali-200,Mali-300, and Mali-400 MP GPUs comprise of a vertex processor and one or more fragment processors. Mali-T600 series GPUs consist of one or more shader cores that can execute vertex or fragment shaders.
granular power requester
Used by a debugger to control powerup and powerdown of specific components within a CoreSight system.
graphics application
A custom program that executes in the Mali graphics system and displays content in a frame buffer for transfer to a display.
graphics driver
A software library implementing OpenGL ES or OpenVG, using graphics accelerator hardware.See Also OpenGL ES driver and OpenVG driver.
Graphics Processor Unit
Graphics Processing Unit: A hardware accelerator for graphics systems using OpenGL ES and OpenVG. The Mali-200,Mali-300, and Mali-400 MP GPUs comprise of a vertex processor and one or more fragment processors. Mali-T600 series GPUs consist of one or more shader cores that can execute vertex or fragment shaders.
half-rate clocking
In an ARM trace macrocell, dividing the trace clock by two so that the TPA can sample trace data signals on both the rising and falling edges of the trace clock. The primary purpose of half-rate clocking is to reduce the signal transition rate on the trace clock of an ASIC for very high-speed systems.
halfword
A 16-bit data item. Halfwords are normally halfword-aligned in ARM systems.
halfword-aligned
Hyphenate halfword-aligned. A data item having a memory address that is divisible by 2.
Halted System Debug
Means that a target can only be debugged when it is not running. With the target stopped, RealView Debugger presents OS awareness information by reading and interpreting target memory.See Also Running System Debug (RSD).
Halting debug
In ARM A-profile and R-profile processors, in AArch32 state, one of two mutually exclusive debug modes. When Halting debug is enabled, core execution halts when a breakpoint or watchpoint is encountered. You can use the debug interface to examine and alter all core state, memory, input and output locations.
halting debug-mode
In ARM A-profile and R-profile processors, in AArch32 state, one of two mutually exclusive debug modes. When Halting debug is enabled, core execution halts when a breakpoint or watchpoint is encountered. You can use the debug interface to examine and alter all core state, memory, input and output locations.
HardFault
HardFault is the generic fault that exists for all classes of fault that cannot be handled by any of the other exception mechanisms.
hardware breakpoint
A breakpoint that is implemented using non-intrusive hardware. Hardware breakpoints are the only method of halting execution on a specific instruction when the instruction is located in Read Only Memory (ROM) or Flash. See Also Chained breakpoint and Data breakpoint.
Head-of-line blocking
In an interconnect, this occurs when a node prevents an important transaction from progressing because a less important transaction blocks the path to the same destination.
hierarchical tiler
Hierarchical Tiler, a type of graphical tiler. Probably not unique to ARM. Used in some of the Mali GPUs. Just two normal words, no capitalisation, no special meaning.
high registers
In AArch32 state, core registers R8-R12, SP, LR, and PC. Some T32 instructions cannot access these registers.
high vectors
In AArch32 state, one of two possible locations for exception vectors. The high vector address range is near the top of the address space, rather than at the bottom.
hint instruction
A hint instruction provides information that the hardware can take advantage of.
Hit-Under-Miss
A buffer that means a memory access can hit in the cache, even though there has been a data miss in the cache.
host
A computer that provides data and other services to another computer. In the context of an ARM debugger, a computer providing debugging services to a target being debugged.
HSD
Means that a target can only be debugged when it is not running. With the target stopped, RealView Debugger presents OS awareness information by reading and interpreting target memory.See Also Running System Debug (RSD).
HT
Hierarchical Tiler, a type of graphical tiler. Probably not unique to ARM. Used in some of the Mali GPUs. Just two normal words, no capitalisation, no special meaning.
HTM
A trace source that makes bus information visible. This information cannot be inferred from the processor using just a trace macrocell. HTM trace can provide: An understanding of multi-layer bus utilization.Software debug. For example, visibility of access to memory areas and data accesses.Bus event detection for trace trigger or filters, and for bus profiling.See Also Advanced High-performance Bus (AHB).
HUM
A buffer that means a memory access can hit in the cache, even though there has been a data miss in the cache.
ICE Extension Unit
A hardware extension to the EmbeddedICE logic that provides more breakpoint units.
IEEE 1149.1
The IEEE Standard that defines TAP. Commonly referred to as JTAG.See IEEE Std 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture specification available from the IEEE Standards Association.
IEM
An energy manager solution consisting of both software and hardware components that function together to prolong battery life in an ARM processor based device.
IGN
An abbreviation for Ignore, when describing the behavior of a register or memory access.
IGNORED
Indicates that the architecture guarantees that the bit or field is not interpreted or modified by hardware, meaning software can safely define how the bit is used When IGNORED appears in body text, it is always in SMALL CAPITALS.
iIntegrator
A range of ARM hardware development platforms. Core modules are available that contain the processor and local memory.See Also Core module.
illegal instruction
Indicates an instruction that is not architecturally defined. It generates an Undefined Instruction exception. See the ARM Architecture Reference Manual for more information.
immediate values
Values that are encoded directly in the instruction and used as numeric data when the instruction is executed. Many ARM and Thumb instructions can be used with an immediate argument.
IMPLEMENTATION DEFINED
Behavior that is not defined by the architecture, but is defined and documented by individual implementations. When implementation defined appears in body text, it is always in small capitals. See Also IMPLEMENTATION SPECIFIC.
IMPLEMENTATION SPECIFIC
In the context of ARM trace macrocells, behavior that is not architecturally defined, and might not be documented by an individual implementation. Used when there are a number of implementation options available and the option chosen does not affect software compatibility. When implementation specific is used with this meaning in body text, it is always in small capitals. Used in Trace documentation only.
imprecise tracing
In an ARM trace macrocell, a filtering configuration where instruction or data tracing can start or finish earlier or later than expected. Most imprecise cases cause tracing to start or finish later than expected.
In-Circuit Emulator
A device that provides access to the signals of a circuit while that circuit is operating, and lets you moderate those signals.
index register
A register specified in some load or store instructions. The value of this register is used as an offset to be added to or subtracted from the base register value to form the virtual address that is sent to memory. Some instruction forms permit the index register value to be shifted before the addition or subtraction.
Input section
Contains code or initialized data or describes a fragment of memory that must be set to zero before the application starts.
Instruction Abort
An indication to the core of an attempted instruction fetch that is not permitted. The Instruction Abort might be generated by access permission checks performed by the memory system on the core, or might be signaled by the memory system. An exception is taken only if the core attempts to execute the instruction. No exception is taken if the core does not execute an instruction that is attempted to fetch or prefetch from a faulting memory location. The AArch64 architecture definitions introduce the term Instruction Abort. Descriptions of AArch32 state use the term Prefetch Abort.
instruction breakpoint
A location in the image containing an instruction that, if executed, activates a breakpoint. The breakpoint activation can be delayed by assigning condition qualifiers, and subsequent execution of the image is determined by any actions assigned to the breakpoint.See Also Conditional breakpoint and Software breakpoint.
instruction set system model
Instruction Set Simulator Model: in the context of RVDS, a set of models that simulate the ARM Cortex family of processors. These models are provided with RVDS.See Also Real Time System Model (RTSM) and Simulator.
Instruction Synchronization Barrier
An operation to ensure that any instruction that comes after the ISB operation is fetched only after the ISB has completed. For more information, see the appropriate ARM Architecture Reference Manual.
Intelligent Energy Manager
An energy manager solution consisting of both software and hardware components that function together to prolong battery life in an ARM processor based device.
intermediate physical address
Do not capitalize the i, p or a of intermediate physical address. In an implementation of virtualization, the address to which a Guest OS maps a virtual address.See Also Virtual Address (VA) and Physical Address (PA).
Intermediate result
In floating-point operation, an internal format that is used to store the result of a calculation before rounding. This format can have a larger exponent field and fraction field than the destination format.
internal scan chain
A series of registers connected together to form a path through a device, used during production testing to import test patterns into internal nodes of the device and export the resulting values.
interworking
In AArch32 state, a method of working that permits branches between software using the A32 and T32 instruction sets.
invalidate
Marking a cache line as being not valid. This must be done whenever the line does not contain a valid cache entry. For example, after a cache flush all lines are invalid.
IPA
Do not capitalize the i, p or a of intermediate physical address. In an implementation of virtualization, the address to which a Guest OS maps a virtual address.See Also Virtual Address (VA) and Physical Address (PA).
IRI
Interrupt Redistribution Infrastructure - one of two parts defined by the GICv3 architecture.
IRQ
IRQ interrupt. nIRQ is one of two interrupt signals on many ARM processors.See Also FIQ.
ISB
An operation to ensure that any instruction that comes after the ISB operation is fetched only after the ISB has completed. For more information, see the appropriate ARM Architecture Reference Manual.
ISSM
Instruction Set Simulator Model: in the context of RVDS, a set of models that simulate the ARM Cortex family of processors. These models are provided with RVDS.See Also Real Time System Model (RTSM) and Simulator.
IT block
In AArch32 state, a block of up to four instructions following a T32 IT (If-Then) instruction. Each instruction in the block is conditional. The condition for each instruction is either the same as or the inverse of the condition specified by the IT instruction.
Jazelle architecture
Some ARM processors before ARMv8 included the Jazelle Extension, to provide hardware execution of some Java bytecodes in AArch32 state, as part of a Java Virtual Machine (JVM) implementation. From ARMv8, the architecture supports only an AArch32 Trivial Jazelle implementation, meaning a JVM must be implemented entirely in software. The Jazelle Extension technology is called Jazelle DBX.
Jazelle DBX
The Jazelle Extension technology is called Jazelle DBX.
Jazelle Extension
Some ARM processors before ARMv8 included the Jazelle Extension, to provide hardware execution of some Java bytecodes in AArch32 state, as part of a Java Virtual Machine (JVM) implementation. From ARMv8, the architecture supports only an AArch32 Trivial Jazelle implementation, meaning a JVM must be implemented entirely in software. The Jazelle Extension technology is called Jazelle DBX.
Jazelle RCT
On an ARM processor, a modification of the T32 instruction set to make it a better target for code generated at runtime. This is also called the T32 Execution Environment (T32EE). From ARMv8, ARM processors do not support Jazelle RCT.
Jazelle Runtime Compilation Target
On an ARM processor, a modification of the T32 instruction set to make it a better target for code generated at runtime. This is also called the T32 Execution Environment (T32EE). From ARMv8, ARM processors do not support Jazelle RCT.
Jazelle state
In AArch32 state, in the Jazelle Instruction set state the core executes Java bytecodes as part of a Java Virtual Machine (JVM). From ARMv8, ARM processors do not support Jazelle state.
Jazelle Technology Enabling Kit
A kit containing source code for integration with a Java Virtual Machine to enable Jazelle DBX on an ARM-based host platform.
job object
In the context of graphics processing, a Mali job system component that provides jobs with required content for Mali GPU execution.
job system back-end
In the context of graphics processing, a Mali job system component that shares some priority handling, but mainly requests jobs from queues and sends job requests to the Mali GPU.
Joint Test Action Group
An IEEE group focussed on silicon chip testing methods. Many debug and programming tools use a Joint Test Action Group (JTAG) interface port to communicate with processors.See IEEE Std 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture specification available from the IEEE Standards Association.
JTAG
An IEEE group focussed on silicon chip testing methods. Many debug and programming tools use a Joint Test Action Group (JTAG) interface port to communicate with processors.See IEEE Std 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture specification available from the IEEE Standards Association.
JTAG Access Port
An optional component of the DAP that provides debugger access to on-chip scan chains.
JTAG interface unit
In the context of ARM RealView tools, a protocol converter that converts low-level commands from RVDS debuggers into JTAG signals to the processor, for example to the EmbeddedICE logic and the ETM.See Also Development Studio 5 (DS-5) and RealView ICE.
JTAG-AP
An optional component of the DAP that provides debugger access to on-chip scan chains.
JTAG-DP
A block that acts as a master on a system bus and provides access to the bus from an external debugger.
JTEK
A kit containing source code for integration with a Java Virtual Machine to enable Jazelle DBX on an ARM-based host platform.
K Virtual Machine
A small implementation of a Java Virtual Machine. It was originally derived from the Sun Spotless Virtual Machine.
KVM
A small implementation of a Java Virtual Machine. It was originally derived from the Sun Spotless Virtual Machine.
little-endian
In the context of the ARM architecture, little-endian is defined as the memory organization in which the most significant byte of a word is at a higher address than the least significant byte.See Also Big-endian.
load view
The address of regions and sections when the image has been loaded into memory but has not yet started execution.See Also Execution view and Scatter-loading.
load/store architecture
A processor architecture where data-processing operations only operate on register contents, not directly on memory contents. The ARM architecture is a Load/Store architecture.
Mali MMU
A full-featured Memory Management Unit (MMU) that is present on Mali GPUs.
MBIST
Memory Built in Self Test
Memory Built-In Self test
The Memory Built-In Self Test (MBIST) interface provides support for manufacturing testing of the memories embedded in a processor. MBIST is the industry-standard method of testing embedded memories. MBIST works by performing sequences of reads and writes to the memory based on test algorithms.
memory coherency
A memory system is coherent if the value read by a data read or instruction fetch is always the value that was most recently written to that location. Memory coherency is difficult when the memory system includes multiple possible physical locations, such as main memory and at least one of a write buffer or one or more caches. See the appropriate ARM Architecture Reference Manual for a more extensive and more rigorous definition of memory coherency.
Memory Management Unit
Provides detailed control of the memory system. Most of the control uses translation tables that are held in memory. An MMU is the major component of an ARM Virtual Memory System Architecture (VMSA).
Memory Protection Unit
A hardware unit that controls a limited number of protection regions in memory. A n MPU is the major component of an ARM Protected Memory System Architecture (PMSA).
MMU
Provides detailed control of the memory system. Most of the control uses translation tables that are held in memory. An MMU is the major component of an ARM Virtual Memory System Architecture (VMSA).
model manager
A software control manager that handles the event transactions between the model and simulator.
Modified Virtual Address
The address produced by the FCSE that is sent to the rest of the memory system to be used in place of the normal virtual address.If the FCSE is absent or disabled, the MVA and the Virtual Address (VA) have the same value. From ARMv6, ARM deprecates any use of the FCSE. The FCSE is optional in the unextended ARMv7 architecture, and obsolete from the introduction of the Multiprocessing Extensions.See Also Fast Context Switch Extension (FCSE).
Monitor debug
In ARM A-profile and R-profile processors, in AArch32 state, one of two mutually exclusive debug modes. When Monitor debug is enabled, a debug event generates a debug exception, that is taken as a Prefetch Abort or Data Abort exception. Breakpoints and watchpoints are examples of debug events.
Monitor debug-mode
In ARM A-profile and R-profile processors, in AArch32 state, one of two mutually exclusive debug modes. When Monitor debug is enabled, a debug event generates a debug exception, that is taken as a Prefetch Abort or Data Abort exception. Breakpoints and watchpoints are examples of debug events.
MPCore
An integrated Symmetric Multiprocessor System (SMP) or Asymmetric Multiprocessor System (AMP) with multiple processors in a single device.
MPU
A hardware unit that controls a limited number of protection regions in memory. A n MPU is the major component of an ARM Protected Memory System Architecture (PMSA).
MTB
The Micro Trace Buffer provides a simple execution trace capability to M-series processors. The MTB provides a lighter option for instruction trace requirements for software development. Unlike the Embedded Trace Macrocell(ETM) or the Program Trace Macrocell(PTM) trace solutions, the MTB does not require dedicated trace connection. However, the amount of trace history provided by the MTB is limited by the size of SRAM allocated for trace operations.
Multi-ICE
A JTAG-based tool for debugging embedded systems.
Multi-layer interconnect
An interconnect scheme similar to a cross-bar switch. Each master on the interconnect has a direct link to each slave that is not shared with other masters. This means each master can process transfers in parallel with other masters. Contention in a multi-layer interconnect only occurs at a payload destination, typically a slave.
Multi-master AHB
Typically a shared, not multi-layer, AHB interconnect scheme. More than one master connects to a single AMBA AHB link. In this case, the bus is implemented with a set of full AMBA AHB master interfaces. Masters that use the AMBA AHB-Lite protocol must connect through a wrapper to supply full AMBA AHB master signals to support multi-master operation.
MVA
The address produced by the FCSE that is sent to the rest of the memory system to be used in place of the normal virtual address.If the FCSE is absent or disabled, the MVA and the Virtual Address (VA) have the same value. From ARMv6, ARM deprecates any use of the FCSE. The FCSE is optional in the unextended ARMv7 architecture, and obsolete from the introduction of the Multiprocessing Extensions.See Also Fast Context Switch Extension (FCSE).
NaN
Not a number. In floating-point operation, NaNs are special floating-point values that can be used when neither a numeric value nor an infinity is appropriate. NaNs can be either:quiet NaNs that propagate through most floating-point operationssignaling NaNs that cause Invalid Operation floating-point exceptions.For more information, see the IEEE 754 standard.
NEON technology
The ARM technology that provides SIMD processing using a dedicated SIMD and floating-point register bank. Registers in this bank can be accessed as 128-bit registers, 64-bit registers, 32-bit registers, 16-bit registers, or 8-bit registers.
Normal world
In software descriptions of the operation of an ARM core, effectively the environments that contain two virtual processors that run on a single core. The Secure World processes operations that are security-critical, and non security-critical operations are performed in the Normal World. Hardware descriptions use Secure state to describe a core that is executing in the Secure World, and Non-secure state to describe a core that is executing in the Normal world.
nSRST
Abbreviation of System Reset. The electronic signal that causes the target system other than the TAP controller to be reset. This signal is known as nSYSRST in some documentation.See Also nTRST and Joint Test Action Group (JTAG).
nTRST
Abbreviation of TAP Reset. The electronic signal that causes the target system TAP controller to be reset. This signal is known as nICERST in some documentation.See Also nSRST and Joint Test Action Group (JTAG).
Offline Compiler
A command line tool that translates vertex shaders and fragment shaders written in the ESSL into binary vertex shaders and binary fragment shaders that you can link and run on the Mali GPU.
offset addressing
Addressing where the memory address is formed by adding an offset to, or subtracting an offset from, a base register value.
on-target compiler
A component of the Mali GPU OpenGL ES 2.0 driver that translates shader source files provided by the graphics application, into binary shader code, at runtime.
OpenGL ES driver
Part of a driver stack that translates OpenGL ES API commands into data and instructions for the Mali GPU. Only the device driver controls the Mali GPU directly.
OpenGL ES Shading Language
A programming language used to create custom shader programs that can be used in a programmable pipeline, on the Mali GPU. You can also use pre-defined library shaders, written in ESSL.
OpenVG driver
Part of a driver stack that translates OpenVG API commands into data and instructions for the Mali GPU. Only the device driver controls the Mali GPU directly.
OS-awareness
OS-awareness is a feature provided by RealView Debugger that enables you to:debug applications running on an embedded OS development platform, such as a Real-Time Operating System (RTOS)present thread information and scope some debugging operations to specific threads.
OTC
A power routing scheme, also referred to as ArtiGrid.See Also ArtiGrid.
output section
A contiguous sequence of input sections that have the same RO, RW, or ZI attributes. The sections are grouped together in larger fragments called regions. The regions are grouped together into the final executable image.See Also Region.
Over The Cell
A power routing scheme, also referred to as ArtiGrid.See Also ArtiGrid.
PA
Do not capitalize the p or a of physical address. PA is the abbreviation of physical address. You can use PA.
page table
A table, held in memory, that contains descriptors that define the mapping between a supplied input address and the corresponding output address, and the properties of the memory region at that address.
PCH
A header file that is precompiled. This avoids the compiler having to compile the file each time it is included by source files.
PE
Core is used to describe a single processing unit. In the application processor area we can further define core as something that has exclusive use of its own program counter (PC). Never use CPU to refer to a core or PE. Do not try to introduce local definitions of CPU to get round this rule.
penalty
The number of cycles in which no useful Execute stage pipeline activity can occur because an instruction flow is different from that assumed or predicted.
PFT
The Program Flow Trace (PFT) architecture assumes that any trace decompressor has a copy of the program being traced, and generally outputs only enough trace for the decompressor to reconstruct the program flow. However, its trace output also enables a decompressor to reconstruct the program flow when it does not have a copy of parts of the program, for example because the program uses self-modifying code.A Program Flow Trace Macrocell (PTM) implements the Program Flow Trace architecture.
physical address
Do not capitalize the p or a of physical address. PA is the abbreviation of physical address. You can use PA.
PISMO
Memory specification for plug-in memory modules.
Platform Independent Storage Module
Memory specification for plug-in memory modules.
PLI
For Verilog simulators, an interface by which foreign code can be included in a simulation. Foreign code is code written in a different language.
PMM
In the context of graphics processors, a software routine that tracks the hardware blocks which can be enabled or disabled to reduce power. The PMM can control a specialized hardware unit, or a third-party power-management device, to power up or down each processor separately.
POP
A performance optimization package for the implementation of an ARM processor using ARM Artisan optimized logic and memory physical IP.See Also G-POP.
Power Management Module
In the context of graphics processors, a software routine that tracks the hardware blocks which can be enabled or disabled to reduce power. The PMM can control a specialized hardware unit, or a third-party power-management device, to power up or down each processor separately.
power-on reset
A Cold reset has the same effect as starting the processor by turning the power on. This clears main memory and many internal settings. Some program failures can lock up the core and require a Cold reset to restart the system.
Powerup reset
A Cold reset has the same effect as starting the processor by turning the power on. This clears main memory and many internal settings. Some program failures can lock up the core and require a Cold reset to restart the system.
PreCompiled Header
A header file that is precompiled. This avoids the compiler having to compile the file each time it is included by source files.
Prefetch Abort
An abort occurs when an illegal memory access causes an exception. An abort can be generated by the hardware that manages memory accesses, or by the external memory system. The hardware that generates the abort might be a Memory Management Unit (MMU) or a Memory Protection Unit (MPU).
prefetching
The process of fetching instructions from memory before the instructions that precede them have finished executing. Prefetching an instruction does not mean that the instruction must be executed.
primitive
In the context of graphics processors, a basic element that the Mali GPU uses, with other primitives, to generate images.
Procedure Call Standard for the Arm Architecture
Defines how registers and the stack are used for subroutine calls.
processing element
The abstract machine defined in the Arm architecture, as documented in an Arm Architecture Reference Manual. A processing element implementation that is compliant with the Arm architecture must conform with the behaviors described in the corresponding Arm Architecture Reference Manual. Do not capitalize the p or e of processing element. PE is the acronym of processing element. You can use PE.
Program Counter
In Arm documentation, PC is the abbreviation of Program Counter.
Program Flow Trace
The Program Flow Trace (PFT) architecture assumes that any trace decompressor has a copy of the program being traced, and generally outputs only enough trace for the decompressor to reconstruct the program flow. However, its trace output also enables a decompressor to reconstruct the program flow when it does not have a copy of parts of the program, for example because the program uses self-modifying code.A Program Flow Trace Macrocell (PTM) implements the Program Flow Trace architecture.
Program Status Register
Holds processor status and control information. The Current Program Status Register (CPSR) is the active PSR that affects processor operation. The Saved Program Status Register (SPSR) is a copy of the CPSR saved by the hardware.
Programming Language Interface
For Verilog simulators, an interface by which foreign code can be included in a simulation. Foreign code is code written in a different language.
protection region
A memory region whose position, size, and other properties are defined by the Memory Protection Unit registers.
Protection Unit
A hardware unit that controls a limited number of protection regions in memory. A n MPU is the major component of an Arm Protected Memory System Architecture (PMSA).
PSR
Holds processor status and control information. The Current Program Status Register (CPSR) is the active PSR that affects processor operation. The Saved Program Status Register (SPSR) is a copy of the CPSR saved by the hardware.
PU
A hardware unit that controls a limited number of protection regions in memory. A n MPU is the major component of an Arm Protected Memory System Architecture (PMSA).
quadword
A 128-bit data item. Quadwords are normally at least word-aligned in Arm systems.
quadword-aligned
Hyphenate quadword-aligned. A data item having a memory address that is divisible by 16.
RAO
Hardware must implement the field as reading as all 1s. Software can rely on the field reading as all 1s. This description can apply to a single bit that reads as 1, or to a field that reads as all 1s.
RAO/SBOP
Read-As-One, Should-Be-One-or-Preserved on writes. Hardware must implement the field as Read-as-One, and must ignore writes to the field. Software can rely on the field reading as all 1s, but must use an SBOP policy to write to the field.This description can apply to a single bit that reads as 1, or to a field that reads as all 1s.See Also Read-As-One (RAO), Should-Be-One-or-Preserved (SBOP).
RAO/WI
Read-As-One, Writes Ignored.Hardware must implement the field as Read-as-One, and must ignore writes to the field.Software can rely on the field reading as all 1s, and on writes being ignored.This description can apply to a single bit that reads as 1, or to a field that reads as all 1s.See Also Read-As-One (RAO).
RAZ
Hardware must implement the field as reading as all 0s.Software can rely on the field reading as all 0s.This description can apply to a single bit that reads as 0, or to a field that reads as all 0s.
RAZ/SBZP
Read-As-Zero, Should-Be-Zero-or-Preserved on writes. Hardware must implement the field as Read-as-Zero, and must ignore writes to the field. Software can rely on the field reading as all 0s, but must use an SBZP policy to write to the field. This description can apply to a single bit that reads as 0, or to a field that reads as all 0s.
RAZ/WI
Read-As-Zero, Writes Ignored. Hardware must implement the field as Read-as-Zero, and must ignore writes to the field. Software can rely on the field reading as all 0s, and on writes being ignored. This description can apply to a single bit that reads as 0, or to a field that reads as all 0s.
RCT
On an Arm processor, a modification of the T32 instruction set to make it a better target for code generated at runtime. This is also called the T32 Execution Environment (T32EE). From Armv8, Arm processors do not support Jazelle RCT.
read
A memory operation that has the semantics of a load.
Read Write Position Independent
In the context of software executing on a core that implements the Arm architecture, read-write code or data that can be placed at any address.
read, modify, write
In a read, modify, write sequence, a value is read to a general-purpose register, the relevant fields updated in that register, and the new value written back.
Read-Allocate
Read-allocation is a technique that is used to deal with data store accesses to caches. In a Read-Allocate cache, the data is simply stored to main memory. Cache lines are only allocated to memory location when data is read or loaded, not when it is written or stored. See also Write-Allocate.
Read-As-One
Hardware must implement the field as reading as all 1s. Software can rely on the field reading as all 1s. This description can apply to a single bit that reads as 1, or to a field that reads as all 1s.
Read-As-Zero
Hardware must implement the field as reading as all 0s.Software can rely on the field reading as all 0s.This description can apply to a single bit that reads as 0, or to a field that reads as all 0s.
Read-Only Position Independent
In the context of software executing on a core that implements the Arm architecture, Read-Only Position Independent describes code or read-only data that can be placed at any address.
Real Time System Model
A software model of a development system, for example, the Emulation Baseboard. The model can run applications at almost full speed. This enables applications and operating systems to be written and debugged without a requirement for actual hardware.
RealMonitor
A small program that, when integrated into your target application or Real-Time Operating System (RTOS), enables you to observe and debug your target while parts of your application continue to run.
RealView Compilation Tools
A suite of tools that, together with supporting documentation and examples, enables you to write and build applications for Arm processors. See Also armcc, armasm.
RealView Debugger
An Arm debugger that enables you to examine and control the execution of software running on a debug target. RealView Debugger is supplied as part of RVDS in both Windows and Red Hat Linux versions.
RealView Debugger Trace
Part of RVDS that extends the debugging capability with the addition of real-time program and data tracing. It is available from the RealView Debugger Code window.See Also RealView Debugger Trace and RealView ICE.
RealView Development Suite
The suite of software development tools, together with supporting documentation and examples, that enable you to write and debug applications for the Arm family of processors.See Also Arm Compiler for DS-5, Arm profiler, Eclipse for DS-5, Development Studio 5 (DS-5), RealView ICE, and RealView Trace and RealView Trace 2.
RealView ICE
An Arm JTAG interface unit for debugging embedded processor cores that uses a DBGTAP or Serial Wire interface.
RealView Instruction Set Simulator
One of the Arm simulators supplied with RVDS. RealView Instruction Set Simulator is a collection of programs that simulate the instruction sets and architecture of various Arm processors. This provides instruction-accurate simulation and enables Arm and Thumb executable programs to be run on non-native hardware. RVISS provides modules that model:the Arm processorthe memory used by the processor. There are alternative predefined models for each of these parts. However, you can create your own models if a supplied model does not meet your requirements.See Also Instruction Set System Model (ISSM) and Real Time System Model (RTSM).
RealView Trace and RealView Trace 2
Work in conjunction with RealView ICE to provide real-time trace functionality for software running in System-on-Chip devices with deeply embedded Arm processors. RealView Trace 2 also supports data streaming directly to Arm Profiler, providing real-time hardware platform profiling.See Also RealView Debugger Trace and RealView ICE.
Redistributor
A Redistributor is a component of the GIC architecture. It is the part of the interrupt routing infrastructure that is connected to the CPU interface, and thereby the PE.
region
In an image, a region is a contiguous sequence of one to three output sections (RO, RW, and ZI). A region typically maps onto a physical memory device, such as ROM, RAM, or peripherals.
remapping
Changing the address of physical memory or devices after an application has started executing. This might be done to permit RAM to replace ROM when the initialization has completed.
replicator
In an Arm trace macrocell, enables two trace sinks to be wired together and to operate independently on the same incoming trace stream. The input trace stream is output onto two independent ATB ports.
RES0
A reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior. Used for fields in register descriptions, and for fields in architecturally-defined data structures that are held in memory, for example in translation table descriptors. Note res0 is not used in descriptions of instruction encodings. Within the architecture, there are some cases where a register bit or bitfield: * Is res0 in some defined architectural context. * Has different defined behavior in a different architectural context.
RES1
A reserved bit or field with Should-Be-One-or-Preserved (SBOP) behavior. Used for fields in register descriptions, and for fields in architecturally-defined data structures that are held in memory, for example in translation table descriptors. Note: res1 is not used in descriptions of instruction encodings. Within the architecture, there are some cases where a register bit or bitfield: * Is res1 in some defined architectural context. * Has different defined behavior in a different architectural context.
RM
An Arm abbreviation for "Round towards Minus Infinity" rounding mode. Take care to include the capitalizations.
RN
This is the Arm equivalent term for the IEEE 754-2008 term "roundTiesToNearest". Take care to include the capitalizations.
root region
In an image, regions having the same load and execution address. A non-root region is a region that must be copied from its load address to its execution address.See Also Region.
ROPI
In the context of software executing on a core that implements the Arm architecture, Read-Only Position Independent describes code or read-only data that can be placed at any address.
Round to Nearest
This is the Arm equivalent term for the IEEE 754-2008 term "roundTiesToNearest". Take care to include the capitalizations.
Round to Nearest with Ties to Away
This is the Arm equivalent term for the IEEE 754-2008 term "roundTiesToAway". Take care to include the capitalizations.
Round towards Minus Infinity
An Arm abbreviation for "Round towards Minus Infinity" rounding mode. Take care to include the capitalizations.
Round towards Plus Infinity
This is the Arm equivalent term for the IEEE 754-2008 term "round Towards Positive Infinity". Take care to include the capitalizations.
Round towards Zero
This is the Arm equivalent term for the IEEE 754-2008 term "roundTowardZero". Take care to include the capitalizations.
rounding mode
In floating-point operation, specifies how the exact result of a floating-point operation is rounded to a value that is representable in the destination format. The IEEE 754 standard defines the required rounding modes for compliant floating-point implementations, and Arm implementations support these rounding modes. See the appropriate Arm Architecture Reference manual for more information about support for the different rounding modes. Note The IEEE 754-2008 standard changes the term Rounding mode to Rounding-direction attribute. Arm documentation continues to use the term Rounding mode, as defined in the IEEE 754-1985 standard.
RP
This is the Arm equivalent term for the IEEE 754-2008 term "round Towards Positive Infinity". Take care to include the capitalizations.
RSD
In the context of software executing on a core that implements the Arm architecture, Read-Only Position Independent describes code or read-only data that can be placed at any address.
RTSM
A software model of a development system, for example, the Emulation Baseboard. The model can run applications at almost full speed. This enables applications and operating systems to be written and debugged without a requirement for actual hardware.
Running System Debug
In the context of software executing on a core that implements the Arm architecture, Read-Only Position Independent describes code or read-only data that can be placed at any address.
RVCT
A suite of tools that, together with supporting documentation and examples, enables you to write and build applications for Arm processors. See Also armcc, armasm.
RVDS
The suite of software development tools, together with supporting documentation and examples, that enable you to write and debug applications for the Arm family of processors.See Also Arm Compiler for DS-5, Arm profiler, Eclipse for DS-5, Development Studio 5 (DS-5), RealView ICE, and RealView Trace and RealView Trace 2.
RVI
An Arm JTAG interface unit for debugging embedded processor cores that uses a DBGTAP or Serial Wire interface.
RVISS
One of the Arm simulators supplied with RVDS. RealView Instruction Set Simulator is a collection of programs that simulate the instruction sets and architecture of various Arm processors. This provides instruction-accurate simulation and enables Arm and Thumb executable programs to be run on non-native hardware. RVISS provides modules that model:the Arm processorthe memory used by the processor. There are alternative predefined models for each of these parts. However, you can create your own models if a supplied model does not meet your requirements.See Also Instruction Set System Model (ISSM) and Real Time System Model (RTSM).
RWPI
In the context of software executing on a core that implements the Arm architecture, read-write code or data that can be placed at any address.
RZ
This is the Arm equivalent term for the IEEE 754-2008 term "roundTowardZero". Take care to include the capitalizations.
Saved Program Status Register
A register used to save the state of the core on taking an exception.
SBO
Hardware must ignore writes to the field. Software should write the field as all 1s. If software writes a value that is not all 1s, it must expect an unpredictable result. This description can apply to a single bit that should be written as 1, or to a field that should be written as all 1s.
SBOP
The Armv7 Large Physical Address Extension modified the definition of SBOP to apply to register fields that are SBOP in some but not all contexts. From the introduction of Armv8 such register fields are described as res1, see RES1. The definition of SBOP given here applies only to fields that are SBOP in all contexts. Hardware must ignore writes to the field. When writing this field, software must either write all 1s to this field, or, if the register is being restored from a previously read state, this field must be written previously read value. If this is not done, then the result is UNPREDICTABLE. This description can apply to a single bit that should be written as its preserved value or as 1, or to a field that should be written as its preserved value or as all 1s.
SBZ
Hardware must ignore writes to the field.Software should write the field as all 0s. If software writes a value that is not all 0s, it must expect an unpredictable result.This description can apply to a single bit that should be written as 0, or to a field that should be written as all 0s.
SBZP
The Large Physical Address Extension modifies the definition of SBZP for register bits that are reallocated by the extension, and as a result are SBZP in some but not all contexts. For more information see the Arm Architecture Reference Manual, Armv7-A and Armv7-R edition. The generic definition of SBZP given here applies only to bits that are not affected by this modification.Hardware must ignore writes to the field.When writing this field, software must either write all 1s to this field, or, if the register is being restored from a previously read state, this field must be written previously read value. If this is not done, then the result is UNPREDICTABLE.This description can apply to a single bit that should be written as its preserved value or as 0, or to a field that should be written as its preserved value or as all 0s.See Also Should-Be-One-or-Preserved (SBOP) and Should-Be-Zero (SBZ).
scatter-loading
Assigning the address and grouping of code and data sections individually rather than using single large blocks.
SCC
Serial Configuration Controller
SDF
A file format that contains timing information to the level of individual bits of buses and is used in SDF back-annotation. An SDF file can be generated in a number of ways, but most commonly from a delay calculator.
Secure world
In software descriptions of the operation of an Arm core, effectively the environments that contain two virtual processors that run on a single core. The Secure World processes operations that are security-critical, and non security-critical operations are performed in the Normal World. Hardware descriptions use Secure state to describe a core that is executing in the Secure World, and Non-secure state to describe a core that is executing in the Non-secure state.
semihosting
A mechanism to communicate Input/Output (I/O) requests from application code to a host workstation running a debugger. For example, you can use semihosting to enable functions in the C library, such as printf() and scanf(), to use the screen and keyboard on the host workstation instead of having a screen and keyboard on the target system.
Serial Configuration Controller
Serial Configuration Controller
Serial Power Controller
Serial Power Controller
Serial Wire Debug
A debug implementation that uses a serial connection between the SoC and a debugger. This connection normally requires a bidirectional data signal and a separate clock signal, rather than the four to six signals required for a JTAG connection.
Serial Wire Debug Port
Serial Wire Debug Port (SW-DP), The interface for Serial Wire Debug.
Shared layer
In general, contains functions used by more than one Mali GPU driver. It contains math functions, texture processing and list utilities.
Should-Be-One
Hardware must ignore writes to the field. Software should write the field as all 1s. If software writes a value that is not all 1s, it must expect an unpredictable result. This description can apply to a single bit that should be written as 1, or to a field that should be written as all 1s.
Should-Be-One-or-Preserved
The Armv7 Large Physical Address Extension modified the definition of SBOP to apply to register fields that are SBOP in some but not all contexts. From the introduction of Armv8 such register fields are described as res1, see RES1. The definition of SBOP given here applies only to fields that are SBOP in all contexts. Hardware must ignore writes to the field. When writing this field, software must either write all 1s to this field, or, if the register is being restored from a previously read state, this field must be written previously read value. If this is not done, then the result is UNPREDICTABLE. This description can apply to a single bit that should be written as its preserved value or as 1, or to a field that should be written as its preserved value or as all 1s.
Should-Be-Zero
Hardware must ignore writes to the field.Software should write the field as all 0s. If software writes a value that is not all 0s, it must expect an unpredictable result.This description can apply to a single bit that should be written as 0, or to a field that should be written as all 0s.
Should-Be-Zero-or-Preserved
The Large Physical Address Extension modifies the definition of SBZP for register bits that are reallocated by the extension, and as a result are SBZP in some but not all contexts. For more information see the Arm Architecture Reference Manual, Armv7-A and Armv7-R edition. The generic definition of SBZP given here applies only to bits that are not affected by this modification.Hardware must ignore writes to the field.When writing this field, software must either write all 1s to this field, or, if the register is being restored from a previously read state, this field must be written previously read value. If this is not done, then the result is UNPREDICTABLE.This description can apply to a single bit that should be written as its preserved value or as 0, or to a field that should be written as its preserved value or as all 0s.See Also Should-Be-One-or-Preserved (SBOP) and Should-Be-Zero (SBZ).
Sign-Off Model
An opaque, compiled simulation model generated from a technology-specific netlist of an Arm processor, derived after gate level synthesis and timing annotation, that you can use in back-annotated gate-level simulations to prove the function and timing behavior of the device. A SOM provides accurate timing simulation of a SoC, and supports simulation using production test vectors from the Automatic Test Pattern Generation (ATPG) tool. It only supports back-annotation using SDF files. The SOM includes timing information but provides slower simulation than a DSM.
SIMD
In the Arm instruction sets, supported SIMD instructions can comprise: Instructions that perform parallel operations on the bytes or halfwords of the Arm core registers. Instructions that perform vector operations. That is, they perform parallel operations on vectors held in multiword registers. Different versions of the Arm architecture support and recommend different instructions for vector operations. See the appropriate version of the Arm Architecture Reference Manual for more information.
simple sequential execution
The behavior of an implementation that fetches, decodes, and completely executes each instruction before proceeding to the next instruction. Such an implementation performs no speculative accesses to memory, including to instruction memory. The implementation does not pipeline any phase of execution. In practice, this is the theoretical execution model that the architecture is based on, and Arm does not expect this model to correspond to a realistic implementation of the architecture.
simple tracepoint
A type of tracepoint that enables you to set trigger points, trace start and end points, or trace ranges for memory and data accesses.See Also Tracepoint.
Single Instruction, Multiple Data
In the Arm instruction sets, supported SIMD instructions can comprise: Instructions that perform parallel operations on the bytes or halfwords of the Arm core registers. Instructions that perform vector operations. That is, they perform parallel operations on vectors held in multiword registers. Different versions of the Arm architecture support and recommend different instructions for vector operations. See the appropriate version of the Arm Architecture Reference Manual for more information.
SMMU
A System MMU is a hardware device designed to provide address translation services and protection functionalities to any DMA capable agent in the system other than the main processor. This includes hardware accelerators such as GPUs and Video Engines (VEs), simple DMA controllers as well as complete sub-systems. The SMMU can be implemented as a standalone device or integrated with an existing DMA capable processing unit.
software breakpoint
A breakpoint that is implemented by replacing an instruction in memory with one that causes the processor to take an exception. Because instruction memory must be altered, software breakpoints cannot be used where instructions are stored in read-only memory. See Also Instruction breakpoint and Data breakpoint.
SOM
An opaque, compiled simulation model generated from a technology-specific netlist of an Arm processor, derived after gate level synthesis and timing annotation, that you can use in back-annotated gate-level simulations to prove the function and timing behavior of the device. A SOM provides accurate timing simulation of a SoC, and supports simulation using production test vectors from the Automatic Test Pattern Generation (ATPG) tool. It only supports back-annotation using SDF files. The SOM includes timing information but provides slower simulation than a DSM.
SP
On Arm cores, SP refers to the stack pointer for the hardware-managed stack, and: In AArch32 state, the SP is register R13 in the general-purpose register file. In AArch64 state, there is a dedicated SP for each implemented Exception level.
SPC
Serial Power Controller
SPICE
Simulation Program with Integrated Circuit Emphasis. An accurate transistor-level electronic circuit simulation tool that can predict how an equivalent real circuit behaves for given circuit conditions.
SPSR
A register used to save the state of the core on taking an exception.
stack pointer
On Arm cores, SP refers to the stack pointer for the hardware-managed stack, and: In AArch32 state, the SP is register R13 in the general-purpose register file. In AArch64 state, there is a dedicated SP for each implemented Exception level.
Standard Delay Format
A file format that contains timing information to the level of individual bits of buses and is used in SDF back-annotation. An SDF file can be generated in a number of ways, but most commonly from a delay calculator.
STM
System Trace Macrocell - A trace source designed primarily for high-bandwidth trace of instrumentation embedded into software. This instrumentation is made up of memory-mapped writes to the STM, which carry information about the behavior of the software.
Strongly-ordered memory
In descriptions before the introduction of Armv8, memory regions with the strongest ordering requirement. From the introduction of Armv8, these regions are described as Device-nGnRnE, indicating that the region is: * non-Gathering - Multiple memory accesses must not be merged into a single access. * non-Reordering - Multiple memory accesses must not be reordered. * no Early Write Acknowledge - A hint to the memory system that only the endpoint of a write access should return an acknowledge for that write access. For more information see the Armv8 Architecture Reference Manual.
subnormal value
The IEEE 754-2008 standard term for a floating-point operand with a zero exponent and a nonzero fraction field. Arm documentation describes these operands as denormal or denormalized, as defined by the IEEE 754-1985 standard. Note Arm floating-point implementations comply with the IEEE 754 requirement that denormalized operands are generated and manipulated with the same precision as normal operands. Plus or minus 0 have zero exponent fields, but are not denormals because there is no loss of accuracy.
Supervisor Call
An instruction that causes the processor to take a Supervisor Call exception.Used by the Arm standard C library to handle semihosting. This was previously called SoftWare Interrupt (SWI).
support code
In a floating-point implementation, system software that complements the hardware VFP implementation. The support code can provide a library of routines that perform operations beyond the scope of the hardware. The support code includes a set of exception handlers to process exceptional conditions in compliance with the IEEE 754 standard.
SVC
An instruction that causes the processor to take a Supervisor Call exception.Used by the Arm standard C library to handle semihosting. This was previously called SoftWare Interrupt (SWI).
SWD
A debug implementation that uses a serial connection between the SoC and a debugger. This connection normally requires a bidirectional data signal and a separate clock signal, rather than the four to six signals required for a JTAG connection.
SW-DP
Serial Wire Debug Port (SW-DP), The interface for Serial Wire Debug.
SWI
An instruction that causes the processor to take a Supervisor Call exception.Used by the Arm standard C library to handle semihosting. This was previously called SoftWare Interrupt (SWI).
SWJ - DP
Serial Wire or JTAG - Debug Port
synchronization primitive
An instruction that is used to ensure memory synchronization, for example LDREX or STREX. See the Arm Architecture Reference Manual for more information.
System Control Space
On Cortex-M series processors, a memory-mapped region from 0xE000E000 to 0xE000EFFF that provides system control and configuration registers, including control of the Nested Vectored Interrupt Controller (NVIC) and debug functions.
System Trace Macrocell
System Trace Macrocell - A trace source designed primarily for high-bandwidth trace of instrumentation embedded into software. This instrumentation is made up of memory-mapped writes to the STM, which carry information about the behavior of the software.
T32
An instruction set that can be used by an Armv8 processor that is in AArch32 execution state. T32 is a variable-length instruction set that uses both 16-bit and 32-bit instruction encodings. It is compatible with the Armv7 Thumb instruction set.See Also AArch32, A32.
T32 instruction
An instruction that can be used by a core that is in AArch32 execution state. T32 is a variable-length instruction set that uses both 16-bit and 32-bit instruction encodings. It is the only instruction supported by Arm M-profile processors. Previously, this instruction set was called the Thumb instruction set.
T32 state
When a core is executing in AArch32 state, if it is in T32 Instruction set state then it executes T32 instructions.
T32EE instruction
One or two halfwords that specify an operation for a core in AArch32 state in T32EE Instruction set state to perform. T32EE is the T32 Execution Environment and the T32EE instruction set is based on the T32 instruction set, with some changes and additions to make it a better target for dynamically generated code, that is, code compiled on the device either shortly before or during execution. Armv8 obsoletes the T32EE instruction set.
T32EE state
In AArch32 state, in the T32EE Instruction set state the core executes the T32EE instruction set.
TAP
The collection of four mandatory and one optional terminals that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. In the JTAG standard, the nTRST signal is optional, but this signal is mandatory in Arm processors because it is used to reset the debug logic. -or- Talent Assessment Programme - Numerical performance review rating
TAP Controller
Logic on a device that enables access to some or all of that device for test purposes. The circuit functionality is defined in IEEE1149.1.See Also Joint Test Action Group (JTAG).
Target
In the context of an Arm debugger, the part of your development platform to which you connect the debugger, and on which debugging operations can be performed. A target can be: *A runnable target, such as a core that implements the Arm architecture. When connected to a runnable target, you can perform execution-related debugging operations on that target, such as stepping and tracing. *A non-runnable CoreSight component. CoreSight components provide a system-wide solution to real-time debug and trace.
TCD
A generic term to describe Trace Port Analyzers, logic analyzers, and on-chip trace buffers.
TCK
The electronic clock signal that times data on the TAP data lines TMS, TDI, and TDO.See Also Test Data Input (TDI) and Test Data Output (TDO).
TCM
An area of low latency memory that provides predictable instruction execution or data load timing, for cases where deterministic performance is required. TCMs are suited to holding:critical routines such as for interrupt handlingscratchpad datadata types whose locality is not suited to cachingcritical data structures, such as interrupt stacks.
TDI
Test Data Input
TDO
Test Data Output (TDO) is the electronic signal output from a TAP controller to the downstream data sink. Usually this connects the last TAP controller to the RealView ICE run control unit.See Also Joint Test Action Group (JTAG), RealView ICE, and TAP Controller.
Test Access Port
The collection of four mandatory and one optional terminals that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. In the JTAG standard, the nTRST signal is optional, but this signal is mandatory in Arm processors because it is used to reset the debug logic. -or- Talent Assessment Programme - Numerical performance review rating
Test Data Input
Test Data Input (TDI) is the electronic signal input to a TAP controller from the data source (upstream). Usually this is seen connecting the RealView ICE run control unit to the first TAP controller.See Also Joint Test Action Group (JTAG), RealView ICE, and TAP Controller.
Test Data Output
Test Data Output (TDO) is the electronic signal output from a TAP controller to the downstream data sink. Usually this connects the last TAP controller to the RealView ICE run control unit.See Also Joint Test Action Group (JTAG), RealView ICE, and TAP Controller.
Texture Descriptor
Data structure used by the Mali GPU to describe one texture map.
Thin Links
A protocol to reduce the number of signals in an AXI point-to-point connection to simplify routing.
Thumb instruction
An instruction that can be used by a core that is in AArch32 execution state. T32 is a variable-length instruction set that uses both 16-bit and 32-bit instruction encodings. It is the only instruction supported by Arm M-profile processors. Previously, this instruction set was called the Thumb instruction set.
Thumb instruction set
An instruction set that can be used by a core that is in AArch32 execution state.
Thumb state
When a core is executing in AArch32 state, if it is in T32 Instruction set state then it executes T32 instructions.
Thumb-2
The technology, introduced in Armv6T2, that extends the Thumb instruction set to a variable-length instructions set that includes both 16-bit and 32-bit instructions.See Also Thumb instruction and ThumbEE instruction.
ThumbEE instruction
One or two halfwords that specify an operation for a core in AArch32 state in T32EE Instruction set state to perform. T32EE is the T32 Execution Environment and the T32EE instruction set is based on the T32 instruction set, with some changes and additions to make it a better target for dynamically generated code, that is, code compiled on the device either shortly before or during execution. Armv8 obsoletes the T32EE instruction set.
ThumbEE state
In AArch32 state, in the T32EE Instruction set state the core executes the T32EE instruction set.
Tightly Coupled Memory
An area of low latency memory that provides predictable instruction execution or data load timing, for cases where deterministic performance is required. TCMs are suited to holding:critical routines such as for interrupt handlingscratchpad datadata types whose locality is not suited to cachingcritical data structures, such as interrupt stacks.
tile buffer
A memory buffer inside the Mail GPU that holds the framebuffer contents for the tile that is currently being rendered. The tile buffer can be accessed without using the memory bus.
TLB
A memory structure containing the results of translation table walks. TLBs help to reduce the average cost of memory accesses.
TLB lockdown
Prevents specific translation table walk results being removed from the TLB. This ensures that accesses to the associated memory areas never cause a translation table walk.
TLX
A protocol to reduce the number of signals in an AXI point-to-point connection to simplify routing.
TMC
Controls the capturing or buffering trace generated by trace sources within a system. The TMC receives trace from an ATB interface and can be configured to perform one of the following: * Route the trace out over an AXI master interface, to allow trace to be captured in system memory or in other peripherals. * Capture the trace in a circular buffer in dedicated SRAM. * Buffer the trace in a First In First Out (FIFO) style, to smooth over peaks in trace bandwidth.
TMS
Test Mode Select.
TPA
A hardware device that captures trace information output on a trace port. This can be a low-cost product designed specifically for trace acquisition, or a logic analyzer.
TPIU
Drains trace data and acts as a bridge between the on-chip trace data and the data stream captured by a TPA.
Trace Capture Device
A generic term to describe Trace Port Analyzers, logic analyzers, and on-chip trace buffers.
trace driver
A remote debug interface target that controls a piece of trace hardware. That is, the trigger macrocell, trace macrocell, and trace capture tool.
trace funnel
In an Arm trace macrocell, a device that combines multiple trace sources onto a single bus.See Also AHB Trace Macrocell (HTM) and CoreSight.
trace hardware
A device that contains an Arm trace macrocell.
Trace Memory Controller
Controls the capturing or buffering trace generated by trace sources within a system. The TMC receives trace from an ATB interface and can be configured to perform one of the following: * Route the trace out over an AXI master interface, to allow trace to be captured in system memory or in other peripherals. * Capture the trace in a circular buffer in dedicated SRAM. * Buffer the trace in a First In First Out (FIFO) style, to smooth over peaks in trace bandwidth.
trace port
A port on a device, such as a processor or ASIC, used to output trace information.
Trace Port Analyzer
A hardware device that captures trace information output on a trace port. This can be a low-cost product designed specifically for trace acquisition, or a logic analyzer.
Trace Port Interface Unit
Drains trace data and acts as a bridge between the on-chip trace data and the data stream captured by a TPA.
Tracepoint unit
In the context of an Arm debugger, a unit within a Chained tracepoint that combines with other tracepoint units to create a complex tracepoint.See Also Chained tracepoint and Tracepoint.
Translation Lookaside Buffer
A memory structure containing the results of translation table walks. TLBs help to reduce the average cost of memory accesses.
translation table
A table, held in memory, that contains descriptors that define the mapping between a supplied input address and the corresponding output address, and the properties of the memory region at that address.
translation table walk
A full translation table lookup. It is performed automatically by hardware.
trap enable bits
For floating-point operation, the trap enable bits determine whether trapped or untrapped exception handling is selected. If trapped exception handling is selected, the way it is carried out is implementation defined.
triangle setup unit
A component of a fragment processor. The triangle setup unit prepares primitives for rendering by calculating the data required to rasterize and shade the primitive.
trigger instruction
In a floating-point implementation that requires a floating-point subarchitecture, a trigger instruction is a floating-point instruction that causes a bounce when it is issued.
Trigger Interface
Part of an Embedded Cross Trigger (ECT) device. In an ECT, the CTI provides the interface between a processor or ETM and the CTM.
TRM
Abbreviation for Technical Reference Manual. -or- Technical Review Meeting
TrustZone Software
A secure software framework that uses the Arm architecture Security Extensions.
TrustZone technology
The hardware and software that enable the integration of enhanced security features throughout a SoC. In Armv6K, Armv7-A and Armv8-M, the Security Extensions implement the TrustZone hardware. In Armv8, EL3 incorporates the TrustZone hardware.
UAL
A common assembler language for the A32 and T32 instruction sets. See the appropriate Arm Architecture Reference Manual for more information.
UMP
Provides a safe way to share memory across processes, drivers and hardware components, possibly using an MMU or MPU for memory protection. The Mali driver stack uses the UMP API for certain optional functionality.
unconditional breakpoint
A breakpoint that does not have a conditional qualifier assigned. The breakpoint activates immediately it is hit, but subsequent image execution is determined by any actions assigned to the breakpoint.See Also Conditional breakpoint and Hardware breakpoint.
UNDEFINED
Indicates cases where an attempt to execute a particular encoding bit pattern generates an exception, that is taken to the current Exception level, or to the default Exception level for taking exceptions if the UNDEFINED encoding was executed at EL0. This applies to: • Any encoding that is not allocated to any instruction. • Any encoding that is defined as never accessible at the current Exception level. • Some cases where an enable, disable, or trap control means an encoding is not accessible at the current Exception level. If the generated exception is taken to an Exception level that is using AArch32 then it is taken as an Undefined Instruction exception. Note: On reset, the default Exception level for taking exceptions from EL0 is EL1. However, an implementation might include controls that can change this, effectively making EL1 inactive. See the description of the Exception model for more information When UNDEFINED appears in body text, it is written in small capitals.
Unified Assembler Language
A common assembler language for the A32 and T32 instruction sets. See the appropriate Arm Architecture Reference Manual for more information.
Unified Memory Provider
Provides a safe way to share memory across processes, drivers and hardware components, possibly using an MMU or MPU for memory protection. The Mali driver stack uses the UMP API for certain optional functionality.
UNK
An abbreviation indicating that software must treat a field as containing an UNKNOWN value.In any implementation, the bit must read as 0, or all 0s for a bit field. Software must not rely on the field reading as zero.
UNK/SBOP
Hardware must implement the field as Read-As-One, and must ignore writes to the field.Software must not rely on the field reading as all 1s, and except for writing back to the register it must treat the value as if it is unknown. Software must use an SBOP policy to write to the field.This description can apply to a single bit that should be written as its preserved value or as 1, or to a field that should be written as its preserved value or as all 1s.See Also Read-As-One (RAO), Should-Be-One-or-Preserved (SBOP), UNKNOWN.
UNK/SBZP
Hardware must implement the field as Read-As-Zero, and must ignore writes to the field.Software must not rely on the field reading as all 0s, and except for writing back to the register it must treat the value as if it is unknown. Software must use an SBZP policy to write to the field.This description can apply to a single bit that should be written as its preserved value or as 0, or to a field that should be written as its preserved value or as all 0s.See Also Read-As-Zero (RAZ), Should-Be-Zero-or-Preserved (SBZP), UNKNOWN.
UNKNOWN
An unknown value does not contain valid data, and can vary from moment to moment, instruction to instruction, and implementation to implementation. An unknown value must not return information that cannot be accessed at the current or a lower level of privilege using instructions that are not unpredictable or constrained unpredictable and do not return unknown values. An unknown value must not be documented or promoted as having a defined value or effect. When unknown appears in body text, it is always in small capitals.
UNP
For an Arm processor, unpredictable means the behavior cannot be relied upon. unpredictable behavior must not perform any function that cannot be performed at the current or a lower level of privilege using instructions that are not unpredictable. unpredictable behavior must not be documented or promoted as having a defined effect.An instruction that is unpredictable can be implemented as undefined. In an implementation that supports Virtualization, the Non-secure execution of unpredictable instructions at a lower level of privilege can be trapped to the hypervisor, provided that at least one instruction that is not unpredictable can be trapped to the hypervisor if executed at that lower level of privilege. For an Arm trace macrocell, unpredictable means that the behavior of the macrocell cannot be relied on. Such conditions have not been validated. When applied to the programming of an event resource, only the output of that event resource is unpredictable. unpredictable behavior can affect the behavior of the entire system, because the trace macrocell can cause the core to enter debug state, and external outputs can be used for other purposes. When unpredictable appears in body text, it is always in small capitals.
UNPREDICTABLE
For an Arm processor, unpredictable means the behavior cannot be relied upon. unpredictable behavior must not perform any function that cannot be performed at the current or a lower level of privilege using instructions that are not unpredictable. unpredictable behavior must not be documented or promoted as having a defined effect.An instruction that is unpredictable can be implemented as undefined. In an implementation that supports Virtualization, the Non-secure execution of unpredictable instructions at a lower level of privilege can be trapped to the hypervisor, provided that at least one instruction that is not unpredictable can be trapped to the hypervisor if executed at that lower level of privilege. For an Arm trace macrocell, unpredictable means that the behavior of the macrocell cannot be relied on. Such conditions have not been validated. When applied to the programming of an event resource, only the output of that event resource is unpredictable. unpredictable behavior can affect the behavior of the entire system, because the trace macrocell can cause the core to enter debug state, and external outputs can be used for other purposes. When unpredictable appears in body text, it is always in small capitals.
VA
Do not capitalize the v or a of virtual address. VA is the abbreviation of virtual address. You can use VA.
VDMA
Video Direct Memory Access. VDMA transfers data in a burst-efficient way to and from system memory.
vectorization
Using multiword registers to hold multiple values of the same type for SIMD processing. For example, software might use doubleword registers to hold four 16-bit unsigned integers. Vectorization also describes the process of adapting software to use SIMD processing. Vector operations are provided by: The VFP instructions in Armv6. The Advanced SIMD instructions from Armv7.
vertex
A set of data defining the properties of one point of a primitive. For example, a point primitive, an endpoint of a line primitive, or a corner of a triangle primitive.
vertex attributes
The data provided by the application, to define a vertex.
vertex loader
A component of the vertex processor that loads vertex attributes from memory and inputs them to the vertex shader unit.
vertex processor
A programmable processor that executes vertex shaders with typical transform and lightning calculations, and generates lists of primitives for a fragment processor to draw.
vertex shader
A program running on a vertex processor or shader core that calculates the position and other characteristics, such as color and texture coordinates, for each vertex.
vertex shader unit
A programmable component of the vertex processor that runs vertex shaders.
VFP
The original name of the extension to the Arm architecture that provided floating-point arithmetic. In Armv7, the extension is called the Floating-point extension. From Armv8, the architecture includes support for floating-point instruction, rather than this being an architecture extension.
VIA
A conductive connection between different layers of an integrated circuit. VIA is always written in uppercase.
victim
A cache line, selected to be discarded to make room for a replacement cache line that is required because of a cache miss. How the victim is selected for eviction is processor-specific. A victim is also known as a cast out.
virtual address
Do not capitalize the v or a of virtual address. VA is the abbreviation of virtual address. You can use VA.
Warm reset
Also known as a core reset. Initializes most of the processor functionality, excluding the debug controller and debug logic. This type of reset is useful if you are using the debugging features of a processor.See also Cold reset.
watch
In an Arm debugger, a watch is a variable or expression that you require the debugger to display at every step or breakpoint so that you can see how its value changes.
word
A 32-bit data item. Words are normally word-aligned in Arm systems.
word-aligned
Hyphenate word-aligned. A data item having a memory address that is divisible by four.
word-invariant
In a word-invariant system, the address of each byte of memory changes when switching between little-endian and big-endian operation, in such a way that the byte with address A in one endianness has address A EOR 3 in the other endianness. As a result, each aligned word of memory always consists of the same four bytes of memory in the same order, regardless of endianness. The change of endianness occurs because of the change to the byte addresses, not because the bytes are rearranged.The Arm architecture supports word-invariant systems in Armv3 and later versions. When word-invariant support is selected, the behavior of load or store instructions with unaligned addresses is instruction-specific, and is in general not the expected behavior for an unaligned access. Arm strongly recommends that word-invariant systems use the endianness that produces the required byte addresses at all times, apart possibly from very early in their reset handlers before they have set up the endianness, and that this early part of the reset handler uses only aligned word memory accesses.See Also Byte-invariant.
Write
Operations that have the semantics of a store. See the Arm Architecture Reference Manual for more information.
write completion
The memory system indicates to the core that a write is complete at a point in the transaction where the memory system can guarantee that the write is observable by all processors in the system. An additional recommendation for Device-nGnRnE memory (Strongly-ordered memory), is that a write to a memory-mapped peripheral is complete only when it reaches that memory-mapped peripheral and therefore can trigger any side effects caused by the memory-mapped peripheral. Write completion is not required to ensure that all side effects are globally visible, although some peripherals might define this as a required property of completed writes.
write interleave capability
For an interface to an interconnect, the number of data-active write transactions for which the interface can transmit data. This is counted from the earliest transaction.
write interleave depth
The number of data-active write transactions for which the interface can receive data.
Write-Access
Write-Access can be configured for to enable writes to areas of memory or particular registers.
Write-Allocate
A data storage method in which, if a memory location to be written is not in cache memory, a cache line is allocated for the memory. The value of that memory is then loaded into the cache from main memory, and the new value for the location is written to cache.
write-back
Refers to 'base register writeback'. Writing back a modified value to the base register used in an address calculation.
Write-Back
A data storage method in which a write updates the cache only and marks the cache line as dirty. External memory is updated only when the line is evicted or explicitly cleaned.
Write-Through
A data storage method in which data is written into the cache and the corresponding main memory location at the same time.
XTSM
This coordinates the operation of multiple XVCs. See Also eXtensible Verification Component (XVC).
XVC
A model that provides system or device stimulus and monitor responses.See Also XVC Test Scenario Manager.
XVC Test Scenario Manager
This coordinates the operation of multiple XVCs. See Also eXtensible Verification Component (XVC).