Sorry, your browser is not supported. We recommend upgrading your browser.
We have done our best to make all the documentation and resources available on old versions of Internet Explorer, but vector image support and the layout may not be optimal. Technical documentation is available as a PDF Download.
Home
Support
Arm Security Updates
Speculative processor vulnerability
Downloads
Downloads
Arm processor security update downloads
Updated on 08/Jun/2020
This page provides download links to important resources, such as whitepapers and mitigation specifications, related to the Arm processor security update.
Cache Speculation Side-channels whitepaper
This whitepaper looks at the susceptibility of Arm implementations following recent research findings from security researchers at Google on new potential cache timing side-channels exploiting processor speculation. This paper also outlines possible mitigations that can be employed for software designed to run on existing Arm processors.
This whitepaper documents the possibilities for a processor to speculatively execute the instructions immediately following what should be a change in control flow, and the mitigations recommended by Arm. This concept has been named Straight-line Speculation.
This guide details the features added as part of the Arm v8.5-A architecture update, which address security issues disclosed by the Google Project Zero team.
Addressing Spectre Variant 1 (CVE-2017-5753) in software
This whitepaper provides a brief overview of the original Spectre Variant 1 attack and discusses some practical mitigation techniques that can be applied.
Firmware interfaces for mitigating cache speculation vulnerabilities
System Software on Arm systems
CVE-2017-5715, also known as Spectre variant 2, is a vulnerability in some Arm CPU designs that might allow an attacker to control the speculative execution flow within a victim execution context and disclose data that is architecturally inaccessible to the attacker. CVE-2018-3639, also known as variant 4, is a vulnerability in some Arm CPU designs that might allow a speculative read of a memory location to read a data value from before the most recent write to that memory location.
Important Information for the Arm website. This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. By disabling cookies, some features of the site will not work.