Arm CoreLink CMN600 and AMBA CHI

  • Delivery method: Face-to-face (Private)

  • Location: Any location

  • Course Length: 2 days

  • Technology Focus: Hardware

  • Cost: Contact us for pricing

  • Provider: Arm

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Summary

At the end of this course, delegates will be able to

  • Apply CHI knowledge to various system design decisions
  • Debug CMN-600 simulations
  • Develop code for CMN-600 address map programming
  • Locate and use debug and trace resources available on CMN-600

Prerequisites:

  • Experience with coherent bus protocols and/or interconnects
  • Basic understanding of Arm architecture memory types will be helpful

Audience:

  • Memory subsystem architects
  • Verification engineers

Length:

2 days

Agenda

Pre-Course OnDemand Training

  • Introduction to Arm – Online Training
  • Introduction to Arm AMBA protocol – Online Training
  • Introduction to Arm AMBA CHI – Online Training

Day 1

  • CHI.B/C overview
  • CHI protocol fundamentals
  • Transaction flows
  • DVM operations
  • Atomics overview
  • Cache stashing
  • Direct Memory Transfer (DMT) and Direct Cache Transfer (DCT)IO Deallocation
  • RAS features
  • Other protocol changes and extensions from CHI.A to CHI.B
  • CHI.C additions

Day 2

  • CMN-600 Overview
  • CMN-600 Cache Coherency
  • CMN-600 System Address Map
  • CMN-600 Initialization
  • CMN-600 Error handling
  • CMN-600 Debug, Trace and PMU

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