Arm CoreLink CMN and AMBA CHI
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Delivery method: Face-to-face (Private)
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Location: Any location
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Course Length: 3 days
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Technology Focus: Hardware
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Cost: Contact us for pricing
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Provider: Arm
Summary
CMN (Coherent Mesh Network) is Arm’s family of CHI-based interconnects supporting hardware cache coherency. This course is customized to cover the specific CMN product of choice.
At the end of this course, delegates will be able to
- Apply CHI knowledge to various system design decisions
- Debug CMN simulations
- Develop code for CMN address map programming
- Locate and use debug and trace resources available on CMN
- Integrate CMN products in a SoC
Prerequisites:
- Experience with coherent bus protocols and/or interconnects is helpful although not required
- Basic understanding of Arm architecture memory types is helpful although not required
Audience:
- Memory subsystem architects
- SoC integration engineers
- SoC Verification engineers
Length:
3 days
Modules:
AMBA CHI protocol detailed overview
- CHI protocol fundamentals
- Transaction flows
- DVM operations
- Atomics overview
- Cache stashing
- Direct Memory Transfer (DMT) and Direct Cache Transfer (DCT) IO Deallocation
- RAS features
- MPAM
- MTE
CMN Hardware
- Overview
- Cache coherency
- System Address Map
- Initialization
- Error Handling
- Debug, Trace and PMU
- Cross-chip support
- QoS features
- ACE-Lite Integration
Socrates CMN Creation
- Socrates overview
- CMN Creation Flow