Arm Corelink Coherent Interconnect and AMBA Protocol

  • Delivery method: Virtual Classroom (Private)

  • Location: Any location

  • Course Length: 3-day

  • Technology Focus: Hardware

  • Cost: Contact us for pricing

  • Provider: Arm

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Arm CoreLink Coherent Interconnects are highly configurable and scalable interconnects for multiple mobile computing use cases from energy efficient to high performance devices. They provide a fully coherent, system-level cache and snoop filter for improved energy efficiency and system performance.

 

At the end of this course, delegates will be able to:

  • Apply AMBA protocol knowledge to various system design decisions
  • Understand the configuration options of the Corelink Coherent Interconnect
  • Configure and integrate a Corelink Coherent Interconnect within their System on Chip
  • Develop code for Corelink Coherent Interconnect address map programming
  • Debug Corelink Coherent Interconnect simulations

 

Prerequisites:

  • Experience with coherent bus protocols and/or interconnects is helpful although not required
  • Basic understanding of Arm architecture memory types is helpful although not required

 

Audience:

  • SoC / Interconnect architects designing the interconnect back plane / memory subsystem.
  • Integration and verification engineers who will need to configure and verify the functionality of the coherent interconnect

 

Length:

3 days

 

Related Products

Corelink CMN-700, CMN-600, CMN-600AE, CI-700, CCI-550, CCI-500, CCI-400

Modules:

For CHI based interconnects:

AMBA5 CHI protocol detailed overview

  • CHI protocol fundamentals
  • Transaction flows
  • DVM operations
  • Atomics overview
  • Cache stashing
  • Direct Memory Transfer (DMT) and Direct Cache Transfer (DCT) IO Deallocation
  • RAS features
  • MPAM
  • MTE

Corelink Coherent Interconnect Hardware

  • Overview
  • Cache coherency
  • System Address Map
  • Initialization
  • Error Handling
  • Debug, Trace and PMU
  • Cross-chip support
  • QoS features
  • ACE-Lite Integration
  • Functional Safety (CMN-600AE only)

For ACE based interconnects:

AMBA4 ACE protocol detailed overview:

  • Channels and Signals
  • Transaction Ordering
  • RACK/WACK
  • Exclusives
  • Barriers
  • DVM Transactions
  • ACE-Lite

Corelink Coherent Interconnect Hardware

  • Overview
  • Functional behaviour
  • QoS
  • Error handling
  • Programming
  • Configuration
  • Integration

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