Arm Cortex-A Physical Implementation
Delivery method: Virtual Classroom (Private)
Location: Any Location
Course Length: 1 day or 2 x 1/2 days
Technology Focus: Hardware
Cost: Contact us for pricing
This course is designed to help implementation engineers with the physical layout and implementation flow specific to their individual piece of Arm Cortex- A Processor IP, such as the Arm Cortex-A78, Cortex X1 or Cortex A65AE. Please note this course will need repeating for each separate processor when working on a multiple processor implementation.
At the end of the course, attendees will be able to
- Describe the design structure and configurable options
- Analyse clock and reset scheme
- Use the implementation methodology
- Apply timing constraints and data flow
- Integrate Power Grid and Low Power implementation
- Learn floorplan and placement guides from Arm experience
- Analyse critical timing and power consumption.
- Integrate DFT and MBIST
- A working knowledge of implementation flows.
- Experience of EDA tool operation.
Engineers who work on a SoC project looking to carry out the physical implementation of Cortex-A processors
Arm DynamIQ, Cortex-X1, A78, A78AE, A78C, A77, A76, A75 A65, A57, A55, A53, A35, A34, A32, A17, A15, A9, A7, A5, CHI, ACE
Two 3-hour Virtual Live Classroom sessions (WebEx) or 1-day private face to face per Arm Processor
- RTL and Library Preparation
- Physical Implementation Flow
- Clocks and Resets
- Asynchronous Bridge and Timing Constraints
- RAM requirement
- Timing Closure
- Major Function Units
- Power Grid Structure and Analysis
- DFT and MBIST