Arm Cortex-A Physical Implementation
Delivery method: Virtual Classroom (Private)
Location: Any Location
Course Length: 1 day or 2 x 1/2 days
Technology Focus: Hardware
Cost: Contact us for pricing
Related products: ARMv8-A, Cortex-A, Neoverse N1 Crypto, Neoverse N1 CPU, Neoverse E1 Crypto, Neoverse E1 CPU, Cortex-A53, Cortex-A55, Cortex-A57, Cortex-A65, Cortex-A73, Cortex-A75, Cortex-A76, Cortex-A76AE, Cortex-A77
This course is designed to help implementation engineers with the physical layout and implementation flow specific to their individual piece of Arm Cortex- A Processor IP, such as the Arm Cortex-A76 or Cortex A65AE. Please note this course will need repeating for each separate processor when working on a multiple processor implementation.
At the end of the course, attendees will be able to
- Describe the design structure and configurable options
- Analyse clock and reset scheme
- Use the implementation methodology
- Apply timing constraints and data flow
- Integrate Power Grid and Low Power implementation
- Learn floorplan and placement guides from Arm experience
- Analyse critical timing and power consumption.
- Integrate DFT and MBIST
- A working knowledge of implementation flows.
- Experience of EDA tool operation.
Engineers who work on a SoC project looking to carry out the physical implementation of Cortex-A processors
Two 3-hour Virtual Live Classroom sessions (WebEx) or 1-day private face to face per Arm Processor
- RTL and Library Preparation
- Physical Implementation Flow
- Clocks and Resets
- Asynchronous Bridge and Timing Constraints
- RAM requirement
- Timing Closure
- Major Function Units
- Power Grid Structure and Analysis
- DFT and MBIST