Arm Cortex-R5 Hardware Design

  • Delivery method: Face-to-face (Private)

  • Location: Any location

  • Course Length: 4 days

  • Technology Focus: Hardware

  • Cost: Contact us for pricing

  • Related products: Cortex-R5, Cortex-R, ARMv7-R, ARMv7-A

  • Provider: Arm



This course is designed for hardware engineers designing systems based around the Arm Cortex-R5 processor core. Including an introduction to the Arm product range and supporting IP, the course covers the Arm core range, programmer's model, instruction set architecture and AMBA on-chip bus architecture. The Cortex-R5 debug architecture is also covered. The course includes a number of worked examples to reinforce the lecture material.


  • Some knowledge of embedded systems
  • Familiarity with digital logic and hardware/ASIC design issues
  • A basic awareness of Arm is useful but not essential


Hardware design engineers who need to understand the issues involved when designing SoC's around the Arm Cortex-R5 processor core.


4 days


  • Architecture Armv7-A/R Overview
  • Armv7-A/R Applications Level Programmers Model
  • Armv7-A/R System Level Programmers Model
  • Armv7-A/R Memory Model
  • Armv7-R Protected Memory System Architecture
  • Armv7-A/R Exceptions
  • Micro-Architecture: Pipelines
  • Micro-Architecture: Memory
  • AXI Protocol
  • Cortex-R5 Overview
  • Cortex-R5 Processor Core
  • Cortex-R5 L1 Sub-Systems
  • Cortex-R5 L2 Interfaces
  • Cortex-R5 Error Handling Schemes
  • Cortex-R5 Clocks, Resets & Power Management
  • Cortex-R5 Implementation
  • Cortex-R5 Initialization
  • Cortex-R5 Interrupts
  • Cortex R5 and Vectored Interrupt Controller - PL192 (Optional)
  • Introduction to CoreSight
  • Cortex-R5 Invasive Debug
  • Cortex-R5 Non-invasive Debug
  • Cortex-R5 Integration
  • Level 2 Cache Controller – L2C-310
  • Generic Interrupt Controller - PL390
  • AHB Protocol
  • AXI Interconnection Architectures
  • NIC301

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