Arm DynamIQ Mobile (ACE) System Design for Cortex A77, A76, A75 and A55
Delivery method: Face-to-face (Private)
Location: Any location
Course Length: 3 days
Technology Focus: Hardware
Cost: Contact us for pricing
Related products: Cortex-A, Architecture, A-profile, Cortex-A75, Cortex-A55, ACE, Cortex-A76, Cortex-A77
This training course covers system-wide configuration and integration topics for DynamIQ-based mobile systems.
At the end of this course, delegates will be able to
- Describe the DynamIQ (DSU), Cortex Processor main functions.
- Integrate the DSU their SoC and configure to match their system requirements, including integrating GIC-600.
- Explain the DynamIQ (DSU) transaction flows and clocking schemes.
- Describe the DSU memory system configuration and behaviour with different memory types.
- Use the DSU and Cortex processor power and reset modes and power transition flows.
- Explain DSU Debug and Trace integration.
- Run the supplied test cases when they get the release package testbenches.
Engineers who work in a SoC project using Cortex-A77, A76, A75 or Cortex-A55 and carry out System Design or IP / SoC verification.
Pre-course Online Training
- Introduction to Arm – Online Training
- Armv8-A Overview – Online Training
- Cortex Processor Behaviors – Online Training
- Introduction to DSU Mobile (ACE) System Design
- DSU Overview (Mobile / ACE)
- Cortex Core Overviews (A77, A76, A75 and A55)
- DSU Transaction Flows for Mobile (ACE) Systems
- Introduction to DSU Memory Types
- Memory System Configuration for DSU Mobile (ACE) Systems
- Coherent Memory System Integration for DSU Mobile (ACE) Systems
- Integrating System-wide ARMv8.2 Support in DSU Mobile (ACE) Systems
- Integrating GIC-600 into a DSU Mobile (ACE) System
- DSU Voltage Domains for Mobile (ACE) Systems
- DSU Clock Domains and Clock Gating for Mobile (ACE) Systems
- DSU Power Domains and Power Modes
- DSU Power Mode Transitions and Reset Scenarios
- DSU Debug and Trace Integration