Designing with CoreSight
Delivery method: Face-to-face (Private)
Location: Any location
Course Length: 2 days
Technology Focus: Hardware
Cost: Contact us for pricing
Related products: Debug and Trace, CoreSight Debug and Trace, Systems IP
This course is intended for engineers designing silicon devices based around ARM cores incorporating the CoreSight debug architecture. The course covers an introduction to CoreSight and then presents detailed material on each aspect of the technology. Please note that the course assumes familiarity with ARM-based designs and with the AMBA/AXI on-chip bus architecture.
- A working knowledge of system-on-chip design.
- Familiarity with ARM technology.
- Familiarity with AMBA/AXI.
Hardware design engineers who need to understand and work with the CoreSight debug architecture
- CoreSight Overview
- CoreSight Buses
- Programmer’s Model
- ETM Specification
- System Discovery
- Control & Access (Debug Access Port, APB Interconnect, Embedded Cross Trigger)
- Trace Sources (CPU Trace Macrocells, System Trace Macrocell, Instrumentation
- Trace Links (Trace Funnel, Replicator, ATB Bridge)
- Trace Sinks (Trace Port Interface Unit, Embedded Trace Buffer, Trace Memory
- CoreSight Time Stamping
- Clocks, Reset & Power Management
- System Design
- CoreSight SoC