Floating Point

The Arm architecture provides high-performance and high-efficiency hardware support for floating-point operations in half-, single-, and double-precision arithmetic. It is fully IEEE-754 compliant with full software library support.

This page describes floating-support relative to Cortex-A and Cortex-R processors. For information relative to Cortex-M, please refer to our DSP for Cortex-M page.

Key applications

The floating-point data type is essential for a wide range of digital signal processing (DSP) applications. Many applications inherently benefit from the dynamic range and precision of floating-point to deal with large data sets or data sets with unpredictable range. Then it makes floating-point usage particularly suitable when computational accuracy is a critical requirement.

Examples of such applications are:

  • Automotive control applications
    • Powertrain
    • ABS, Traction control & active suspension

  • 3D Graphics
    • Digital consumer products
    • Set-top boxes and games consoles

  • Imaging
    • Laser printers, still digital cameras, and digital video cameras

  • Industrial control systems
    • Motion controls

Specification

Armv8-A/R architecture

The Armv8 architecture supports single-precision (32-bit) and double-precision (64-bit) floating-point data types and arithmetic as defined by the IEEE 754 floating-point standard. It also supports the half-precision (16-bit) floating-point data type for data storage, by supporting conversions between single-precision and half-precision data types and double-precision and half-precision data types. When Armv8.2-FP16 is implemented, it also supports the half-precision floating-point data type for data-processing operations. 

The Advanced SIMD (NEON) instructions provide packed Single Instruction Multiple Data (SIMD) and single-element scalar operations, and support:

• Single-precision and double-precision arithmetic in AArch64 state  

• Single-precision arithmetic only in AArch32 state

• When Armv8.2-FP16 is implemented, half-precision arithmetic is supported in AArch64 and AArch32 states

Floating-point support in AArch64 state SIMD is IEEE 754-2008 compliant with:

• Configurable rounding modes

• Configurable Default NaN behavior

• Configurable Flush-to-zero behavior

Floating-point computation using AArch32 Advanced SIMD instructions remains unchanged from Armv7.

Scalable Vector Extension (SVE) for Armv8-A

SVE is the next-generation SIMD instruction set for AArch64 that introduces the architectural features for High Performance Computing (HPC). SVE extends the floating-point capability of the Armv8-A architecture targeting A64 ISA only.

Armv7-A/R and previous architectures

Prior to Armv8-A/R, the Arm architecture distinguishes between scalar (VFP) and Advanced SIMD extension (NEON) floating-point support.

Up to Armv7-A/R architecture (included), floating-point architecture is a floating-point coprocessor extension to the instruction set architectures. For historic reasons, the Floating-point Extension is also called the VFP Extension.

VFPv1 Obsolete. Details are available on request from Arm. 
VFPv2 An optional extension to:
the Arm instruction set in the Armv5TE, Armv5TEJ, Armv6, and Armv6K architectures
the Arm and Thumb instruction sets in the Armv6T2 architecture
VFPv3 An optional extension to the Arm, Thumb, and ThumbEE instruction sets in the Armv7-A and Armv7-R profiles. VFPv3 can be implemented with either 32 or 16 doubleword registers. VFPv3U is a variant of VFPv3 that supports the trapping of floating-point exceptions to support code.
VFPv3 with Half-precision Extension
 VFPv3 and VFPv3U can be extended by the optional Half-precision Extension, that provides conversion functions in both directions between half-precision floating-point and single-precision floating-point.
VFPv4 An optional extension to the Arm, Thumb, and ThumbEE instruction sets in the Armv7-A and Armv7-R profiles. VFPv4U is a variant of VFPv4 that supports the trapping of floating-point exceptions to support code. VFPv4 and VFPv4U add both the Half-precision Extension and the fused multiply-add instructions to the features of VFPv3. VFPv4 can be implemented with either 32 or 16 doubleword registers.

The Armv7-A/R Advanced SIMD extension (NEON) offers single-precision floating-point support and performs IEEE 754 floating-point arithmetic with the following restrictions:

• Denormalized numbers are flushed to zero, see Flush-to-zero on page A1-51

• Only default NaNs are supported

• The Round to Nearest rounding mode is used

• Untrapped floating-point exception handling is used for all floating-point exceptions

See section A1.4 Architecture extensions of Arm Architecture Reference Manual Armv7-A and Armv7-R edition for a full description.

Related tools

Arm DS-5 Development Studio provides an end-to-end suite of tools for C/C++ software development for Arm-based platforms. DS-5 fully supports Arm floating-point architecture for programming and debugging.