Arm Frame Buffer Compression (AFBC)
Employing AFBC throughout the SoC saves significant system bandwidth and power
The Arm Frame Buffer Compression (AFBC) protocol addresses the difficulty of creating increasingly more complex designs within the thermal limit of a mobile device. One of the most bandwidth intensive use cases is video post processing. In many use cases, the GPU is required to read a video and apply effects when using video streams as textures in 2D or 3D scenes. In such cases it reduces the overall system level bandwidth and power cost of transferring spatially coordinated image data throughout the system by up to 50%.
A lossless image compression protocol and format, AFBC minimizes the amount of data transferred between IP blocks within a SoC. Its lossless compression ratios are comparable with other leading standards but with the added benefit of fine grained random access, which importantly allows for the application of AFBC throughout other IP blocks within your SoC design.
Lossless compression format
Format preserves original image exactly (bit exact).
Compression ratios comparable to other lossless compression standards.
Supported in current and future Mali IP
Across GPU, Video and Display processors.
Licensable for integration with 3rd party media IP.
Reduces SoC energy consumption
Due to significant reduction in bandwidth.
AFBC can be added at zero area cost.
Bounded worst-case compression ratios
Random access down to 4x4 block level.
Support for both YUV and RGB formats
YUV compression ratio of typically 50%
Bandwidth Reduction in Media System
When AFBC is used in an SoC, the Video Processor will simply write out the video streams in the compressed format and the GPU will read them and only uncompress them in the on-chip memory. Exactly the same optimization will be applied to the output buffers intended for the screen. Whether it is the GPU or Video Processor producing the final frame buffers, they will be compressed so that the Display Processor will read these in the AFBC format and only uncompress when moving to the display memory. AFBC is described in more detail in Ola’s blog Mali-V500 video processor: reducing memory bandwidth with AFBC.
The diagram shows the reduction of video decoder memory bandwidth provided by AFBC when decoding a 4K H.264 video stream. The blue curve shows the bandwidth when AFBC is not used (for reference). The green curve shows the bandwidth of Mali-V500 when AFBC is used for internal reference frame compression only and the red curve shows the bandwidth when AFBC compression is used for the output frame as well (with an AFBC-enabled display processor).
Bandwidth reductions are considerable. The power savings associated with this depend entirely on the design of the SoC and the memory system used, but power for bandwidth used is commonly of the order of 150mW per GByte/s in mobile systems, so the savings are very worthwhile.
Reducing system memory bandwidth is of course, just one element of Arm's overall power reduction strategy — are many other things we do, both large and small, that lead to us having a low-power solution. However, the introduction of AFBC is a major contribution to reducing overall SoC power.