## NEON Intrinsics

Click on the intrinsic name to display more information about the intrinsic. To search for an intrinsic, enter the name of the intrinsic in the search box. As you type, the matching intrinsics will be displayed.

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- NEON Intrinsics Reference

Click on the intrinsic name to display more information about the intrinsic. To search for an intrinsic, enter the name of the intrinsic in the search box. As you type, the matching intrinsics will be displayed.

Add.

ADD Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Add.

ADD Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Add.

ADD Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Add.

ADD Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Add.

ADD Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Add.

ADD Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Add.

ADD Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Add.

ADD Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Add.

ADD Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Add.

ADD Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Add.

ADD Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Add.

ADD Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Add.

ADD Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Add.

ADD Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Add.

ADD Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Add.

ADD Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Floating-point add.

FADD Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point add.

FADD Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point add.

FADD Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point add.

FADD Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Add.

ADD Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Add.

ADD Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Signed add long.

SADDL Vd.8H,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8H → result

v7/A32/A64

Signed add long.

SADDL Vd.4S,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4S → result

v7/A32/A64

Signed add long.

SADDL Vd.2D,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2D → result

v7/A32/A64

Unsigned add long.

UADDL Vd.8H,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8H → result

v7/A32/A64

Unsigned add long.

UADDL Vd.4S,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4S → result

v7/A32/A64

Unsigned add long.

UADDL Vd.2D,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2D → result

v7/A32/A64

Signed add long.

SADDL2 Vd.8H,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.8H → result

A64

Signed add long.

SADDL2 Vd.4S,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.4S → result

A64

Signed add long.

SADDL2 Vd.2D,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.2D → result

A64

Unsigned add long.

UADDL2 Vd.8H,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.8H → result

A64

Unsigned add long.

UADDL2 Vd.4S,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.4S → result

A64

Unsigned add long.

UADDL2 Vd.2D,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.2D → result

A64

Signed add wide.

SADDW Vd.8H,Vn.8H,Vm.8B

a → Vn.8H

b → Vm.8B

Vd.8H → result

v7/A32/A64

Signed add wide.

SADDW Vd.4S,Vn.4S,Vm.4H

a → Vn.4S

b → Vm.4H

Vd.4S → result

v7/A32/A64

Signed add wide.

SADDW Vd.2D,Vn.2D,Vm.2S

a → Vn.2D

b → Vm.2S

Vd.2D → result

v7/A32/A64

Unsigned add wide.

UADDW Vd.8H,Vn.8H,Vm.8B

a → Vn.8H

b → Vm.8B

Vd.8H → result

v7/A32/A64

Unsigned add wide.

UADDW Vd.4S,Vn.4S,Vm.4H

a → Vn.4S

b → Vm.4H

Vd.4S → result

v7/A32/A64

Unsigned add wide.

UADDW Vd.2D,Vn.2D,Vm.2S

a → Vn.2D

b → Vm.2S

Vd.2D → result

v7/A32/A64

Signed add wide.

SADDW2 Vd.8H,Vn.8H,Vm.16B

a → Vn.8H

b → Vm.16B

Vd.8H → result

A64

Signed add wide.

SADDW2 Vd.4S,Vn.4S,Vm.8H

a → Vn.4S

b → Vm.8H

Vd.4S → result

A64

Signed add wide.

SADDW2 Vd.2D,Vn.2D,Vm.4S

a → Vn.2D

b → Vm.4S

Vd.2D → result

A64

Unsigned add wide.

UADDW2 Vd.8H,Vn.8H,Vm.16B

a → Vn.8H

b → Vm.16B

Vd.8H → result

A64

Unsigned add wide.

UADDW2 Vd.4S,Vn.4S,Vm.8H

a → Vn.4S

b → Vm.8H

Vd.4S → result

A64

Unsigned add wide.

UADDW2 Vd.2D,Vn.2D,Vm.4S

a → Vn.2D

b → Vm.4S

Vd.2D → result

A64

Signed halving add.

SHADD Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Signed halving add.

SHADD Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Signed halving add.

SHADD Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Signed halving add.

SHADD Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Signed halving add.

SHADD Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Signed halving add.

SHADD Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Unsigned halving add.

UHADD Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Unsigned halving add.

UHADD Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Unsigned halving add.

UHADD Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Unsigned halving add.

UHADD Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Unsigned halving add.

UHADD Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Unsigned halving add.

UHADD Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Signed rounding halving add.

SRHADD Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Signed rounding halving add.

SRHADD Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Signed rounding halving add.

SRHADD Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Signed rounding halving add.

SRHADD Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Signed rounding halving add.

SRHADD Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Signed rounding halving add.

SRHADD Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Unsigned rounding halving add.

URHADD Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Unsigned rounding halving add.

URHADD Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Unsigned rounding halving add.

URHADD Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Unsigned rounding halving add.

URHADD Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Unsigned rounding halving add.

URHADD Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Unsigned rounding halving add.

URHADD Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Signed saturating add.

SQADD Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Signed saturating add.

SQADD Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Signed saturating add.

SQADD Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Signed saturating add.

SQADD Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Signed saturating add.

SQADD Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Signed saturating add.

SQADD Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Signed saturating add.

SQADD Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Signed saturating add.

SQADD Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Unsigned saturating add.

UQADD Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Unsigned saturating add.

UQADD Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Unsigned saturating add.

UQADD Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Unsigned saturating add.

UQADD Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Unsigned saturating add.

UQADD Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Unsigned saturating add.

UQADD Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Unsigned saturating add.

UQADD Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Unsigned saturating add.

UQADD Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Signed saturating add.

SQADD Bd,Bn,Bm

a → Bn

b → Bm

Bd → result

A64

Signed saturating add.

SQADD Hd,Hn,Hm

a → Hn

b → Hm

Hd → result

A64

Signed saturating add.

SQADD Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Signed saturating add.

SQADD Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Unsigned saturating add.

UQADD Bd,Bn,Bm

a → Bn

b → Bm

Bd → result

A64

Unsigned saturating add.

UQADD Hd,Hn,Hm

a → Hn

b → Hm

Hd → result

A64

Unsigned saturating add.

UQADD Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Unsigned saturating add.

UQADD Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Signed saturating accumulate of unsigned value.

SUQADD Vd.8B,Vn.8B

a → Vd.8B

b → Vn.8B

Vd.8B → result

A64

Signed saturating accumulate of unsigned value.

SUQADD Vd.16B,Vn.16B

a → Vd.16B

b → Vn.16B

Vd.16B → result

A64

Signed saturating accumulate of unsigned value.

SUQADD Vd.4H,Vn.4H

a → Vd.4H

b → Vn.4H

Vd.4H → result

A64

Signed saturating accumulate of unsigned value.

SUQADD Vd.8H,Vn.8H

a → Vd.8H

b → Vn.8H

Vd.8H → result

A64

Signed saturating accumulate of unsigned value.

SUQADD Vd.2S,Vn.2S

a → Vd.2S

b → Vn.2S

Vd.2S → result

A64

Signed saturating accumulate of unsigned value.

SUQADD Vd.4S,Vn.4S

a → Vd.4S

b → Vn.4S

Vd.4S → result

A64

Signed saturating accumulate of unsigned value.

SUQADD Dd,Dn

a → Dd

b → Dn

Dd → result

A64

Signed saturating accumulate of unsigned value.

SUQADD Vd.2D,Vn.2D

a → Vd.2D

b → Vn.2D

Vd.2D → result

A64

Signed saturating accumulate of unsigned value.

SUQADD Bd,Bn

a → Bd

b → Bn

Bd → result

A64

Signed saturating accumulate of unsigned value.

SUQADD Hd,Hn

a → Hd

b → Hn

Hd → result

A64

Signed saturating accumulate of unsigned value.

SUQADD Sd,Sn

a → Sd

b → Sn

Sd → result

A64

Signed saturating accumulate of unsigned value.

SUQADD Dd,Dn

a → Dd

b → Dn

Dd → result

A64

Unsigned saturating accumulate of signed value.

USQADD Vd.8B,Vn.8B

a → Vd.8B

b → Vn.8B

Vd.8B → result

A64

Unsigned saturating accumulate of signed value.

USQADD Vd.16B,Vn.16B

a → Vd.16B

b → Vn.16B

Vd.16B → result

A64

Unsigned saturating accumulate of signed value.

USQADD Vd.4H,Vn.4H

a → Vd.4H

b → Vn.4H

Vd.4H → result

A64

Unsigned saturating accumulate of signed value.

USQADD Vd.8H,Vn.8H

a → Vd.8H

b → Vn.8H

Vd.8H → result

A64

Unsigned saturating accumulate of signed value.

USQADD Vd.2S,Vn.2S

a → Vd.2S

b → Vn.2S

Vd.2S → result

A64

Unsigned saturating accumulate of signed value.

USQADD Vd.4S,Vn.4S

a → Vd.4S

b → Vn.4S

Vd.4S → result

A64

Unsigned saturating accumulate of signed value.

USQADD Dd,Dn

a → Dd

b → Dn

Dd → result

A64

Unsigned saturating accumulate of signed value.

USQADD Vd.2D,Vn.2D

a → Vd.2D

b → Vn.2D

Vd.2D → result

A64

Unsigned saturating accumulate of signed value.

USQADD Bd,Bn

a → Bd

b → Bn

Bd → result

A64

Unsigned saturating accumulate of signed value.

USQADD Hd,Hn

a → Hd

b → Hn

Hd → result

A64

Unsigned saturating accumulate of signed value.

USQADD Sd,Sn

a → Sd

b → Sn

Sd → result

A64

Unsigned saturating accumulate of signed value.

USQADD Dd,Dn

a → Dd

b → Dn

Dd → result

A64

Add returning high narrow.

ADDHN Vd.8B,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8B → result

v7/A32/A64

Add returning high narrow.

ADDHN Vd.4H,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4H → result

v7/A32/A64

Add returning high narrow.

ADDHN Vd.2S,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2S → result

v7/A32/A64

Add returning high narrow.

ADDHN Vd.8B,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8B → result

v7/A32/A64

Add returning high narrow.

ADDHN Vd.4H,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4H → result

v7/A32/A64

Add returning high narrow.

ADDHN Vd.2S,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2S → result

v7/A32/A64

Add returning high narrow.

ADDHN2 Vd.16B,Vn.8H,Vm.8H

r → Vd.8B

a → Vn.8H

b → Vm.8H

Vd.16B → result

A64

Add returning high narrow.

ADDHN2 Vd.8H,Vn.4S,Vm.4S

r → Vd.4H

a → Vn.4S

b → Vm.4S

Vd.8H → result

A64

Add returning high narrow.

ADDHN2 Vd.4S,Vn.2D,Vm.2D

r → Vd.2S

a → Vn.2D

b → Vm.2D

Vd.4S → result

A64

Add returning high narrow.

ADDHN2 Vd.16B,Vn.8H,Vm.8H

r → Vd.8B

a → Vn.8H

b → Vm.8H

Vd.16B → result

A64

Add returning high narrow.

ADDHN2 Vd.8H,Vn.4S,Vm.4S

r → Vd.4H

a → Vn.4S

b → Vm.4S

Vd.8H → result

A64

Add returning high narrow.

ADDHN2 Vd.4S,Vn.2D,Vm.2D

r → Vd.2S

a → Vn.2D

b → Vm.2D

Vd.4S → result

A64

Rounding add returning high narrow.

RADDHN Vd.8B,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8B → result

v7/A32/A64

Rounding add returning high narrow.

RADDHN Vd.4H,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4H → result

v7/A32/A64

Rounding add returning high narrow.

RADDHN Vd.2S,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2S → result

v7/A32/A64

Rounding add returning high narrow.

RADDHN Vd.8B,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8B → result

v7/A32/A64

Rounding add returning high narrow.

RADDHN Vd.4H,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4H → result

v7/A32/A64

Rounding add returning high narrow.

RADDHN Vd.2S,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2S → result

v7/A32/A64

Rounding add returning high narrow.

RADDHN2 Vd.16B,Vn.8H,Vm.8H

r → Vd.8B

a → Vn.8H

b → Vm.8H

Vd.16B → result

A64

Rounding add returning high narrow.

RADDHN2 Vd.8H,Vn.4S,Vm.4S

r → Vd.4H

a → Vn.4S

b → Vm.4S

Vd.8H → result

A64

Rounding add returning high narrow.

RADDHN2 Vd.4S,Vn.2D,Vm.2D

r → Vd.2S

a → Vn.2D

b → Vm.2D

Vd.4S → result

A64

Rounding add returning high narrow.

RADDHN2 Vd.16B,Vn.8H,Vm.8H

r → Vd.8B

a → Vn.8H

b → Vm.8H

Vd.16B → result

A64

Rounding add returning high narrow.

RADDHN2 Vd.8H,Vn.4S,Vm.4S

r → Vd.4H

a → Vn.4S

b → Vm.4S

Vd.8H → result

A64

Rounding add returning high narrow.

RADDHN2 Vd.4S,Vn.2D,Vm.2D

r → Vd.2S

a → Vn.2D

b → Vm.2D

Vd.4S → result

A64

Multiply.

MUL Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Multiply.

MUL Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Multiply.

MUL Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Multiply.

MUL Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Multiply.

MUL Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Multiply.

MUL Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Multiply.

MUL Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Multiply.

MUL Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Multiply.

MUL Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Multiply.

MUL Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Multiply.

MUL Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Multiply.

MUL Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point multiply.

FMUL Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point multiply.

FMUL Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Polynomial multiply.

PMUL Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Polynomial multiply.

PMUL Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Floating-point multiply.

FMUL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point multiply.

FMUL Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Floating-point multiply extended (by element).

FMULX Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

A64

Floating-point multiply extended (by element).

FMULX Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

A64

Floating-point multiply extended (by element).

FMULX Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point multiply extended (by element).

FMULX Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Floating-point multiply extended (by element).

FMULX Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Floating-point multiply extended (by element).

FMULX Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point multiply extended (by element).

FMULX Vd.2S,Vn.2S,Vm.S[lane]

a → Vn.2S

v → Vm.2S

0 << lane << 1

Vd.2S → result

A64

Floating-point multiply extended (by element).

FMULX Vd.4S,Vn.4S,Vm.S[lane]

a → Vn.4S

v → Vm.2S

0 << lane << 1

Vd.4S → result

A64

Floating-point multiply extended (by element).

FMULX Dd,Dn,Vm.D[lane]

a → Dn

v → Vm.1D

0 << lane << 0

Dd → result

A64

Floating-point multiply extended (by element).

FMULX Vd.2D,Vn.2D,Vm.D[lane]

a → Vn.2D

v → Vm.1D

0 << lane << 0

Vd.2D → result

A64

Floating-point multiply extended (by element).

FMULX Sd,Sn,Vm.S[lane]

a → Sn

v → Vm.2S

0 << lane << 1

Sd → result

A64

Floating-point multiply extended (by element).

FMULX Dd,Dn,Vm.D[lane]

a → Dn

v → Vm.1D

0 << lane << 0

Dd → result

A64

Floating-point multiply extended (by element).

FMULX Vd.2S,Vn.2S,Vm.S[lane]

a → Vn.2S

v → Vm.4S

0 << lane << 3

Vd.2S → result

A64

Floating-point multiply extended (by element).

FMULX Vd.4S,Vn.4S,Vm.S[lane]

a → Vn.4S

v → Vm.4S

0 << lane << 3

Vd.4S → result

A64

Floating-point multiply extended (by element).

FMULX Dd,Dn,Vm.D[lane]

a → Dn

v → Vm.2D

0 << lane << 1

Dd → result

A64

Floating-point multiply extended (by element).

FMULX Vd.2D,Vn.2D,Vm.D[lane]

a → Vn.2D

v → Vm.2D

0 << lane << 1

Vd.2D → result

A64

Floating-point multiply extended (by element).

FMULX Sd,Sn,Vm.S[lane]

a → Sn

v → Vm.4S

0 << lane << 3

Sd → result

A64

Floating-point multiply extended (by element).

FMULX Dd,Dn,Vm.D[lane]

a → Dn

v → Vm.2D

0 << lane << 1

Dd → result

A64

Floating-point divide.

FDIV Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

A64

Floating-point divide.

FDIV Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

A64

Floating-point divide.

FDIV Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point divide.

FDIV Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Multiply-add to accumulator.

MLA Vd.8B,Vn.8B,Vm.8B

a → Vd.8B

b → Vn.8B

c → Vm.8B

Vd.8B → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.16B,Vn.16B,Vm.16B

a → Vd.16B

b → Vn.16B

c → Vm.16B

Vd.16B → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.4H,Vn.4H,Vm.4H

a → Vd.4H

b → Vn.4H

c → Vm.4H

Vd.4H → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.8H,Vn.8H,Vm.8H

a → Vd.8H

b → Vn.8H

c → Vm.8H

Vd.8H → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.2S,Vn.2S,Vm.2S

a → Vd.2S

b → Vn.2S

c → Vm.2S

Vd.2S → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.4S,Vn.4S,Vm.4S

a → Vd.4S

b → Vn.4S

c → Vm.4S

Vd.4S → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.8B,Vn.8B,Vm.8B

a → Vd.8B

b → Vn.8B

c → Vm.8B

Vd.8B → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.16B,Vn.16B,Vm.16B

a → Vd.16B

b → Vn.16B

c → Vm.16B

Vd.16B → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.4H,Vn.4H,Vm.4H

a → Vd.4H

b → Vn.4H

c → Vm.4H

Vd.4H → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.8H,Vn.8H,Vm.8H

a → Vd.8H

b → Vn.8H

c → Vm.8H

Vd.8H → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.2S,Vn.2S,Vm.2S

a → Vd.2S

b → Vn.2S

c → Vm.2S

Vd.2S → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.4S,Vn.4S,Vm.4S

a → Vd.4S

b → Vn.4S

c → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point multiply-add to accumulator.

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1

a → N/A

b → N/A

c → N/A

N/A → result

v7/A32/A64

Floating-point multiply-add to accumulator.

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 3

a → N/A

b → N/A

c → N/A

N/A → result

v7/A32/A64

Floating-point multiply-add to accumulator.

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0

a → N/A

b → N/A

c → N/A

N/A → result

A64

Floating-point multiply-add to accumulator.

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1

a → N/A

b → N/A

c → N/A

N/A → result

A64

Signed multiply-add long.

SMLAL Vd.8H,Vn.8B,Vm.8B

a → Vd.8H

b → Vn.8B

c → Vm.8B

Vd.8H → result

v7/A32/A64

Signed multiply-add long.

SMLAL Vd.4S,Vn.4H,Vm.4H

a → Vd.4S

b → Vn.4H

c → Vm.4H

Vd.4S → result

v7/A32/A64

Signed multiply-add long.

SMLAL Vd.2D,Vn.2S,Vm.2S

a → Vd.2D

b → Vn.2S

c → Vm.2S

Vd.2D → result

v7/A32/A64

Unsigned multiply-add long.

UMLAL Vd.8H,Vn.8B,Vm.8B

a → Vd.8H

b → Vn.8B

c → Vm.8B

Vd.8H → result

v7/A32/A64

Unsigned multiply-add long.

UMLAL Vd.4S,Vn.4H,Vm.4H

a → Vd.4S

b → Vn.4H

c → Vm.4H

Vd.4S → result

v7/A32/A64

Unsigned multiply-add long.

UMLAL Vd.2D,Vn.2S,Vm.2S

a → Vd.2D

b → Vn.2S

c → Vm.2S

Vd.2D → result

v7/A32/A64

Signed multiply-add long.

SMLAL2 Vd.8H,Vn.16B,Vm.16B

a → Vd.8H

b → Vn.16B

c → Vm.16B

Vd.8H → result

A64

Signed multiply-add long.

SMLAL2 Vd.4S,Vn.8H,Vm.8H

a → Vd.4S

b → Vn.8H

c → Vm.8H

Vd.4S → result

A64

Signed multiply-add long.

SMLAL2 Vd.2D,Vn.4S,Vm.4S

a → Vd.2D

b → Vn.4S

c → Vm.4S

Vd.2D → result

A64

Unsigned multiply-add long.

UMLAL2 Vd.8H,Vn.16B,Vm.16B

a → Vd.8H

b → Vn.16B

c → Vm.16B

Vd.8H → result

A64

Unsigned multiply-add long.

UMLAL2 Vd.4S,Vn.8H,Vm.8H

a → Vd.4S

b → Vn.8H

c → Vm.8H

Vd.4S → result

A64

Unsigned multiply-add long.

UMLAL2 Vd.2D,Vn.4S,Vm.4S

a → Vd.2D

b → Vn.4S

c → Vm.4S

Vd.2D → result

A64

Multiply-subtract from accumulator.

MLS Vd.8B,Vn.8B,Vm.8B

a → Vd.8B

b → Vn.8B

c → Vm.8B

Vd.8B → result

v7/A32/A64

Multiply-subtract from accumulator.

MLS Vd.16B,Vn.16B,Vm.16B

a → Vd.16B

b → Vn.16B

c → Vm.16B

Vd.16B → result

v7/A32/A64

Multiply-subtract from accumulator.

MLS Vd.4H,Vn.4H,Vm.4H

a → Vd.4H

b → Vn.4H

c → Vm.4H

Vd.4H → result

v7/A32/A64

Multiply-subtract from accumulator.

MLS Vd.8H,Vn.8H,Vm.8H

a → Vd.8H

b → Vn.8H

c → Vm.8H

Vd.8H → result

v7/A32/A64

Multiply-subtract from accumulator.

MLS Vd.2S,Vn.2S,Vm.2S

a → Vd.2S

b → Vn.2S

c → Vm.2S

Vd.2S → result

v7/A32/A64

Multiply-subtract from accumulator.

MLS Vd.4S,Vn.4S,Vm.4S

a → Vd.4S

b → Vn.4S

c → Vm.4S

Vd.4S → result

v7/A32/A64

Multiply-subtract from accumulator.

MLS Vd.8B,Vn.8B,Vm.8B

a → Vd.8B

b → Vn.8B

c → Vm.8B

Vd.8B → result

v7/A32/A64

Multiply-subtract from accumulator.

MLS Vd.16B,Vn.16B,Vm.16B

a → Vd.16B

b → Vn.16B

c → Vm.16B

Vd.16B → result

v7/A32/A64

Multiply-subtract from accumulator.

MLS Vd.4H,Vn.4H,Vm.4H

a → Vd.4H

b → Vn.4H

c → Vm.4H

Vd.4H → result

v7/A32/A64

Multiply-subtract from accumulator.

MLS Vd.8H,Vn.8H,Vm.8H

a → Vd.8H

b → Vn.8H

c → Vm.8H

Vd.8H → result

v7/A32/A64

Multiply-subtract from accumulator.

MLS Vd.2S,Vn.2S,Vm.2S

a → Vd.2S

b → Vn.2S

c → Vm.2S

Vd.2S → result

v7/A32/A64

Multiply-subtract from accumulator.

MLS Vd.4S,Vn.4S,Vm.4S

a → Vd.4S

b → Vn.4S

c → Vm.4S

Vd.4S → result

v7/A32/A64

Multiply-subtract from accumulator.

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1

a → N/A

b → N/A

c → N/A

N/A → result

v7/A32/A64

Multiply-subtract from accumulator.

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 3

a → N/A

b → N/A

c → N/A

N/A → result

v7/A32/A64

Multiply-subtract from accumulator.

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0

a → N/A

b → N/A

c → N/A

N/A → result

A64

Multiply-subtract from accumulator.

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1

a → N/A

b → N/A

c → N/A

N/A → result

A64

Signed multiply-subtract long.

SMLSL Vd.8H,Vn.8B,Vm.8B

a → Vd.8H

b → Vn.8B

c → Vm.8B

Vd.8H → result

v7/A32/A64

Signed multiply-subtract long.

SMLSL Vd.4S,Vn.4H,Vm.4H

a → Vd.4S

b → Vn.4H

c → Vm.4H

Vd.4S → result

v7/A32/A64

Signed multiply-subtract long.

SMLSL Vd.2D,Vn.2S,Vm.2S

a → Vd.2D

b → Vn.2S

c → Vm.2S

Vd.2D → result

v7/A32/A64

Unsigned multiply-subtract long.

UMLSL Vd.8H,Vn.8B,Vm.8B

a → Vd.8H

b → Vn.8B

c → Vm.8B

Vd.8H → result

v7/A32/A64

Unsigned multiply-subtract long.

UMLSL Vd.4S,Vn.4H,Vm.4H

a → Vd.4S

b → Vn.4H

c → Vm.4H

Vd.4S → result

v7/A32/A64

Unsigned multiply-subtract long.

UMLSL Vd.2D,Vn.2S,Vm.2S

a → Vd.2D

b → Vn.2S

c → Vm.2S

Vd.2D → result

v7/A32/A64

Signed multiply-subtract long.

SMLSL2 Vd.8H,Vn.16B,Vm.16B

a → Vd.8H

b → Vn.16B

c → Vm.16B

Vd.8H → result

A64

Signed multiply-subtract long.

SMLSL2 Vd.4S,Vn.8H,Vm.8H

a → Vd.4S

b → Vn.8H

c → Vm.8H

Vd.4S → result

A64

Signed multiply-subtract long.

SMLSL2 Vd.2D,Vn.4S,Vm.4S

a → Vd.2D

b → Vn.4S

c → Vm.4S

Vd.2D → result

A64

Unsigned multiply-subtract long.

UMLSL2 Vd.8H,Vn.16B,Vm.16B

a → Vd.8H

b → Vn.16B

c → Vm.16B

Vd.8H → result

A64

Unsigned multiply-subtract long.

UMLSL2 Vd.4S,Vn.8H,Vm.8H

a → Vd.4S

b → Vn.8H

c → Vm.8H

Vd.4S → result

A64

Unsigned multiply-subtract long.

UMLSL2 Vd.2D,Vn.4S,Vm.4S

a → Vd.2D

b → Vn.4S

c → Vm.4S

Vd.2D → result

A64

Floating-point fused multiply-add to accumulator.

FMLA Vd.2S,Vn.2S,Vm.2S

a → Vd.2S

b → Vn.2S

c → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point fused multiply-add to accumulator.

FMLA Vd.4S,Vn.4S,Vm.4S

a → Vd.4S

b → Vn.4S

c → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point fused multiply-add.

FMADD Dd,Dn,Dm,Da

a → Da

b → Dn

c → Dm

Dd → result

A64

Floating-point fused multiply-add to accumulator.

FMLA Vd.2D,Vn.2D,Vm.2D

a → Vd.2D

b → Vn.2D

c → Vm.2D

Vd.2D → result

A64

Floating-point fused multiply-add to accumulator.

FMLA Vd.2S,Vn.2S,Vm.S[lane]

a → Vd.2S

b → Vn.2S

v → Vm.2S

0 << lane << 1

Vd.2S → result

A64

Floating-point fused multiply-add to accumulator.

FMLA Vd.4S,Vn.4S,Vm.S[lane]

a → Vd.4S

b → Vn.4S

v → Vm.2S

0 << lane << 1

Vd.4S → result

A64

Floating-point fused multiply-add to accumulator.

FMLA Dd,Dn,Vm.D[lane]

a → Dd

b → Dn

v → Vm.1D

0 << lane << 0

Dd → result

A64

Floating-point fused multiply-add to accumulator.

FMLA Vd.2D,Vn.2D,Vm.D[lane]

a → Vd.2D

b → Vn.2D

v → Vm.1D

0 << lane << 0

Vd.2D → result

A64

Floating-point fused multiply-add to accumulator.

FMLA Sd,Sn,Vm.S[lane]

a → Sd

b → Sn

v → Vm.2S

0 << lane << 1

Sd → result

A64

Floating-point fused multiply-add to accumulator.

FMLA Dd,Dn,Vm.D[lane]

a → Dd

b → Dn

v → Vm.1D

0 << lane << 0

Dd → result

A64

Floating-point fused multiply-add to accumulator.

FMLA Vd.2S,Vn.2S,Vm.S[lane]

a → Vd.2S

b → Vn.2S

v → Vm.4S

0 << lane << 3

Vd.2S → result

A64

Floating-point fused multiply-add to accumulator.

FMLA Vd.4S,Vn.4S,Vm.S[lane]

a → Vd.4S

b → Vn.4S

v → Vm.4S

0 << lane << 3

Vd.4S → result

A64

Floating-point fused multiply-add to accumulator.

FMLA Dd,Dn,Vm.D[lane]

a → Dd

b → Dn

v → Vm.2D

0 << lane << 1

Dd → result

A64

Floating-point fused multiply-add to accumulator.

FMLA Vd.2D,Vn.2D,Vm.D[lane]

a → Vd.2D

b → Vn.2D

v → Vm.2D

0 << lane << 1

Vd.2D → result

A64

Floating-point fused multiply-add to accumulator.

FMLA Sd,Sn,Vm.S[lane]

a → Sd

b → Sn

v → Vm.4S

0 << lane << 3

Sd → result

A64

Floating-point fused multiply-add to accumulator.

FMLA Dd,Dn,Vm.D[lane]

a → Dd

b → Dn

v → Vm.2D

0 << lane << 1

Dd → result

A64

Floating-point fused multiply-subtract from accumulator.

FMLS Vd.2S,Vn.2S,Vm.2S

a → Vd.2S

b → Vn.2S

c → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point fused multiply-subtract from accumulator.

FMLS Vd.4S,Vn.4S,Vm.4S

a → Vd.4S

b → Vn.4S

c → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point fused multiply-subtract.

FMSUB Dd,Dn,Dm,Da

a → Da

b → Dn

c → Dm

Dd → result

A64

Floating-point fused multiply-subtract from accumulator.

FMLS Vd.2D,Vn.2D,Vm.2D

a → Vd.2D

b → Vn.2D

c → Vm.2D

Vd.2D → result

A64

Floating-point fused multiply-subtract from accumulator.

FMLS Vd.2S,Vn.2S,Vm.S[lane]

a → Vd.2S

b → Vn.2S

v → Vm.2S

0 << lane << 1

Vd.2S → result

A64

Floating-point fused multiply-subtract from accumulator.

FMLS Vd.4S,Vn.4S,Vm.S[lane]

a → Vd.4S

b → Vn.4S

v → Vm.2S

0 << lane << 1

Vd.4S → result

A64

Floating-point fused multiply-subtract from accumulator.

FMLS Dd,Dn,Vm.D[lane]

a → Dd

b → Dn

v → Vm.1D

0 << lane << 0

Dd → result

A64

Floating-point fused multiply-subtract from accumulator.

FMLS Vd.2D,Vn.2D,Vm.D[lane]

a → Vd.2D

b → Vn.2D

v → Vm.1D

0 << lane << 0

Vd.2D → result

A64

Floating-point fused multiply-subtract from accumulator.

FMLS Sd,Sn,Vm.S[lane]

a → Sd

b → Sn

v → Vm.2S

0 << lane << 1

Sd → result

A64

Floating-point fused multiply-subtract from accumulator.

FMLS Dd,Dn,Vm.D[lane]

a → Dd

b → Dn

v → Vm.1D

0 << lane << 0

Dd → result

A64

Floating-point fused multiply-subtract from accumulator.

FMLS Vd.2S,Vn.2S,Vm.S[lane]

a → Vd.2S

b → Vn.2S

v → Vm.4S

0 << lane << 3

Vd.2S → result

A64

Floating-point fused multiply-subtract from accumulator.

FMLS Vd.4S,Vn.4S,Vm.S[lane]

a → Vd.4S

b → Vn.4S

v → Vm.4S

0 << lane << 3

Vd.4S → result

A64

Floating-point fused multiply-subtract from accumulator.

FMLS Dd,Dn,Vm.D[lane]

a → Dd

b → Dn

v → Vm.2D

0 << lane << 1

Dd → result

A64

Floating-point fused multiply-subtract from accumulator.

FMLS Vd.2D,Vn.2D,Vm.D[lane]

a → Vd.2D

b → Vn.2D

v → Vm.2D

0 << lane << 1

Vd.2D → result

A64

Floating-point fused multiply-subtract from accumulator.

FMLS Sd,Sn,Vm.S[lane]

a → Sd

b → Sn

v → Vm.4S

0 << lane << 3

Sd → result

A64

Floating-point fused multiply-subtract from accumulator.

FMLS Dd,Dn,Vm.D[lane]

a → Dd

b → Dn

v → Vm.2D

0 << lane << 1

Dd → result

A64

Signed saturating doubling multiply returning high half.

SQDMULH Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Signed saturating doubling multiply returning high half.

SQDMULH Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Signed saturating doubling multiply returning high half.

SQDMULH Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Signed saturating doubling multiply returning high half.

SQDMULH Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Signed saturating doubling multiply returning high half.

SQDMULH Hd,Hn,Hm

a → Hn

b → Hm

Hd → result

A64

Signed saturating doubling multiply returning high half.

SQDMULH Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Signed saturating rounding doubling multiply returning high half.

SQRDMULH Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Signed saturating rounding doubling multiply returning high half.

SQRDMULH Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Signed saturating rounding doubling multiply returning high half.

SQRDMULH Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Signed saturating rounding doubling multiply returning high half.

SQRDMULH Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Signed saturating rounding doubling multiply returning high half.

SQRDMULH Hd,Hn,Hm

a → Hn

b → Hm

Hd → result

A64

Signed saturating rounding doubling multiply returning high half.

SQRDMULH Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Signed saturating doubling multiply-add long.

SQDMLAL Vd.4S,Vn.4H,Vm.4H

a → Vd.4S

b → Vn.4H

c → Vm.4H

Vd.4S → result

v7/A32/A64

Signed saturating doubling multiply-add long.

SQDMLAL Vd.2D,Vn.2S,Vm.2S

a → Vd.2D

b → Vn.2S

c → Vm.2S

Vd.2D → result

v7/A32/A64

Signed saturating doubling multiply-add long.

SQDMLAL Sd,Hn,Hm

a → Sd

b → Hn

c → Hm

Sd → result

A64

Signed saturating doubling multiply-add long.

SQDMLAL Dd,Sn,Sm

a → Dd

b → Sn

c → Sm

Dd → result

A64

Signed saturating doubling multiply-add long.

SQDMLAL2 Vd.4S,Vn.8H,Vm.8H

a → Vd.4S

b → Vn.8H

c → Vm.8H

Vd.4S → result

A64

Signed saturating doubling multiply-add long.

SQDMLAL2 Vd.2D,Vn.4S,Vm.4S

a → Vd.2D

b → Vn.4S

c → Vm.4S

Vd.2D → result

A64

Signed saturating doubling multiply-subtract long.

SQDMLSL Vd.4S,Vn.4H,Vm.4H

a → Vd.4S

b → Vn.4H

c → Vm.4H

Vd.4S → result

v7/A32/A64

Signed saturating doubling multiply-subtract long.

SQDMLSL Vd.2D,Vn.2S,Vm.2S

a → Vd.2D

b → Vn.2S

c → Vm.2S

Vd.2D → result

v7/A32/A64

Signed saturating doubling multiply-subtract long.

SQDMLSL Sd,Hn,Hm

a → Sd

b → Hn

c → Hm

Sd → result

A64

Signed saturating doubling multiply-subtract long.

SQDMLSL Dd,Sn,Sm

a → Dd

b → Sn

c → Sm

Dd → result

A64

Signed saturating doubling multiply-subtract long.

SQDMLSL2 Vd.4S,Vn.8H,Vm.8H

a → Vd.4S

b → Vn.8H

c → Vm.8H

Vd.4S → result

A64

Signed saturating doubling multiply-subtract long.

SQDMLSL2 Vd.2D,Vn.4S,Vm.4S

a → Vd.2D

b → Vn.4S

c → Vm.4S

Vd.2D → result

A64

Signed multiply long.

SMULL Vd.8H,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8H → result

v7/A32/A64

Signed multiply long.

SMULL Vd.4S,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4S → result

v7/A32/A64

Signed multiply long.

SMULL Vd.2D,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2D → result

v7/A32/A64

Unsigned multiply long.

UMULL Vd.8H,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8H → result

v7/A32/A64

Unsigned multiply long.

UMULL Vd.4S,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4S → result

v7/A32/A64

Unsigned multiply long.

UMULL Vd.2D,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2D → result

v7/A32/A64

Polynomial multiply long.

PMULL Vd.8H,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8H → result

v7/A32/A64

Signed multiply long.

SMULL2 Vd.8H,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.8H → result

A64

Signed multiply long.

SMULL2 Vd.4S,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.4S → result

A64

Signed multiply long.

SMULL2 Vd.2D,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.2D → result

A64

Unsigned multiply long.

UMULL2 Vd.8H,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.8H → result

A64

Unsigned multiply long.

UMULL2 Vd.4S,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.4S → result

A64

Unsigned multiply long.

UMULL2 Vd.2D,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.2D → result

A64

Polynomial multiply long.

PMULL2 Vd.8H,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.8H → result

A64

Signed saturating doubling multiply long.

SQDMULL Vd.4S,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4S → result

v7/A32/A64

Signed saturating doubling multiply long.

SQDMULL Vd.2D,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2D → result

v7/A32/A64

Signed saturating doubling multiply long.

SQDMULL Sd,Hn,Hm

a → Hn

b → Hm

Sd → result

A64

Signed saturating doubling multiply long.

SQDMULL Dd,Sn,Sm

a → Sn

b → Sm

Dd → result

A64

Signed saturating doubling multiply long.

SQDMULL2 Vd.4S,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.4S → result

A64

Signed saturating doubling multiply long.

SQDMULL2 Vd.2D,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.2D → result

A64

Subtract.

SUB Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Subtract.

SUB Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Subtract.

SUB Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Subtract.

SUB Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Subtract.

SUB Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Subtract.

SUB Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Subtract.

SUB Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Subtract.

SUB Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Subtract.

SUB Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Subtract.

SUB Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Subtract.

SUB Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Subtract.

SUB Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Subtract.

SUB Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Subtract.

SUB Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Subtract.

SUB Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Subtract.

SUB Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Floating-point subtract.

FSUB Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point subtract.

FSUB Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point subtract.

FSUB Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point subtract.

FSUB Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Subtract.

SUB Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Subtract.

SUB Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Signed subtract long.

SSUBL Vd.8H,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8H → result

v7/A32/A64

Signed subtract long.

SSUBL Vd.4S,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4S → result

v7/A32/A64

Signed subtract long.

SSUBL Vd.2D,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2D → result

v7/A32/A64

Unsigned subtract long.

USUBL Vd.8H,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8H → result

v7/A32/A64

Unsigned subtract long.

USUBL Vd.4S,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4S → result

v7/A32/A64

Unsigned subtract long.

USUBL Vd.2D,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2D → result

v7/A32/A64

Signed subtract long.

SSUBL2 Vd.8H,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.8H → result

A64

Signed subtract long.

SSUBL2 Vd.4S,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.4S → result

A64

Signed subtract long.

SSUBL2 Vd.2D,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.2D → result

A64

Unsigned subtract long.

USUBL2 Vd.8H,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.8H → result

A64

Unsigned subtract long.

USUBL2 Vd.4S,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.4S → result

A64

Unsigned subtract long.

USUBL2 Vd.2D,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.2D → result

A64

Signed subtract wide.

SSUBW Vd.8H,Vn.8H,Vm.8B

a → Vn.8H

b → Vm.8B

Vd.8H → result

v7/A32/A64

Signed subtract wide.

SSUBW Vd.4S,Vn.4S,Vm.4H

a → Vn.4S

b → Vm.4H

Vd.4S → result

v7/A32/A64

Signed subtract wide.

SSUBW Vd.2D,Vn.2D,Vm.2S

a → Vn.2D

b → Vm.2S

Vd.2D → result

v7/A32/A64

Unsigned subtract wide.

USUBW Vd.8H,Vn.8H,Vm.8B

a → Vn.8H

b → Vm.8B

Vd.8H → result

v7/A32/A64

Unsigned subtract wide.

USUBW Vd.4S,Vn.4S,Vm.4H

a → Vn.4S

b → Vm.4H

Vd.4S → result

v7/A32/A64

Unsigned subtract wide.

USUBW Vd.2D,Vn.2D,Vm.2S

a → Vn.2D

b → Vm.2S

Vd.2D → result

v7/A32/A64

Signed subtract wide.

SSUBW2 Vd.8H,Vn.8H,Vm.16B

a → Vn.8H

b → Vm.16B

Vd.8H → result

A64

Signed subtract wide.

SSUBW2 Vd.4S,Vn.4S,Vm.8H

a → Vn.4S

b → Vm.8H

Vd.4S → result

A64

Signed subtract wide.

SSUBW2 Vd.2D,Vn.2D,Vm.4S

a → Vn.2D

b → Vm.4S

Vd.2D → result

A64

Unsigned subtract wide.

USUBW2 Vd.8H,Vn.8H,Vm.16B

a → Vn.8H

b → Vm.16B

Vd.8H → result

A64

Unsigned subtract wide.

USUBW2 Vd.4S,Vn.4S,Vm.8H

a → Vn.4S

b → Vm.8H

Vd.4S → result

A64

Unsigned subtract wide.

USUBW2 Vd.2D,Vn.2D,Vm.4S

a → Vn.2D

b → Vm.4S

Vd.2D → result

A64

Signed halving subtract.

SHSUB Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Signed halving subtract.

SHSUB Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Signed halving subtract.

SHSUB Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Signed halving subtract.

SHSUB Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Signed halving subtract.

SHSUB Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Signed halving subtract.

SHSUB Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Unsigned halving subtract.

UHSUB Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Unsigned halving subtract.

UHSUB Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Unsigned halving subtract.

UHSUB Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Unsigned halving subtract.

UHSUB Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Unsigned halving subtract.

UHSUB Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Unsigned halving subtract.

UHSUB Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Signed saturating subtract.

SQSUB Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Signed saturating subtract.

SQSUB Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Signed saturating subtract.

SQSUB Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Signed saturating subtract.

SQSUB Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Signed saturating subtract.

SQSUB Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Signed saturating subtract.

SQSUB Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Signed saturating subtract.

SQSUB Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Signed saturating subtract.

SQSUB Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Unsigned saturating subtract.

UQSUB Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Unsigned saturating subtract.

UQSUB Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Unsigned saturating subtract.

UQSUB Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Unsigned saturating subtract.

UQSUB Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Unsigned saturating subtract.

UQSUB Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Unsigned saturating subtract.

UQSUB Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Unsigned saturating subtract.

UQSUB Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Unsigned saturating subtract.

UQSUB Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Signed saturating subtract.

SQSUB Bd,Bn,Bm

a → Bn

b → Bm

Bd → result

A64

Signed saturating subtract.

SQSUB Hd,Hn,Hm

a → Hn

b → Hm

Hd → result

A64

Signed saturating subtract.

SQSUB Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Signed saturating subtract.

SQSUB Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Unsigned saturating subtract.

UQSUB Bd,Bn,Bm

a → Bn

b → Bm

Bd → result

A64

Unsigned saturating subtract.

UQSUB Hd,Hn,Hm

a → Hn

b → Hm

Hd → result

A64

Unsigned saturating subtract.

UQSUB Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Unsigned saturating subtract.

UQSUB Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Subtract returning high narrow.

SUBHN Vd.8B,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8B → result

v7/A32/A64

Subtract returning high narrow.

SUBHN Vd.4H,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4H → result

v7/A32/A64

Subtract returning high narrow.

SUBHN Vd.2S,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2S → result

v7/A32/A64

Subtract returning high narrow.

SUBHN Vd.8B,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8B → result

v7/A32/A64

Subtract returning high narrow.

SUBHN Vd.4H,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4H → result

v7/A32/A64

Subtract returning high narrow.

SUBHN Vd.2S,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2S → result

v7/A32/A64

Subtract returning high narrow.

SUBHN2 Vd.16B,Vn.8H,Vm.8H

r → Vd.8B

a → Vn.8H

b → Vm.8H

Vd.16B → result

A64

Subtract returning high narrow.

SUBHN2 Vd.8H,Vn.4S,Vm.4S

r → Vd.4H

a → Vn.4S

b → Vm.4S

Vd.8H → result

A64

Subtract returning high narrow.

SUBHN2 Vd.4S,Vn.2D,Vm.2D

r → Vd.2S

a → Vn.2D

b → Vm.2D

Vd.4S → result

A64

Subtract returning high narrow.

SUBHN2 Vd.16B,Vn.8H,Vm.8H

r → Vd.8B

a → Vn.8H

b → Vm.8H

Vd.16B → result

A64

Subtract returning high narrow.

SUBHN2 Vd.8H,Vn.4S,Vm.4S

r → Vd.4H

a → Vn.4S

b → Vm.4S

Vd.8H → result

A64

Subtract returning high narrow.

SUBHN2 Vd.4S,Vn.2D,Vm.2D

r → Vd.2S

a → Vn.2D

b → Vm.2D

Vd.4S → result

A64

Rounding subtract returning high narrow.

RSUBHN Vd.8B,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8B → result

v7/A32/A64

Rounding subtract returning high narrow.

RSUBHN Vd.4H,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4H → result

v7/A32/A64

Rounding subtract returning high narrow.

RSUBHN Vd.2S,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2S → result

v7/A32/A64

Rounding subtract returning high narrow.

RSUBHN Vd.8B,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8B → result

v7/A32/A64

Rounding subtract returning high narrow.

RSUBHN Vd.4H,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4H → result

v7/A32/A64

Rounding subtract returning high narrow.

RSUBHN Vd.2S,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2S → result

v7/A32/A64

Rounding subtract returning high narrow.

RSUBHN2 Vd.16B,Vn.8H,Vm.8H

r → Vd.8B

a → Vn.8H

b → Vm.8H

Vd.16B → result

A64

Rounding subtract returning high narrow.

RSUBHN2 Vd.8H,Vn.4S,Vm.4S

r → Vd.4H

a → Vn.4S

b → Vm.4S

Vd.8H → result

A64

Rounding subtract returning high narrow.

RSUBHN2 Vd.4S,Vn.2D,Vm.2D

r → Vd.2S

a → Vn.2D

b → Vm.2D

Vd.4S → result

A64

Rounding subtract returning high narrow.

RSUBHN2 Vd.16B,Vn.8H,Vm.8H

r → Vd.8B

a → Vn.8H

b → Vm.8H

Vd.16B → result

A64

Rounding subtract returning high narrow.

RSUBHN2 Vd.8H,Vn.4S,Vm.4S

r → Vd.4H

a → Vn.4S

b → Vm.4S

Vd.8H → result

A64

Rounding subtract returning high narrow.

RSUBHN2 Vd.4S,Vn.2D,Vm.2D

r → Vd.2S

a → Vn.2D

b → Vm.2D

Vd.4S → result

A64

Compare bitwise equal to zero.

CMEQ Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Compare bitwise equal to zero.

CMEQ Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Compare bitwise equal to zero.

CMEQ Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Compare bitwise equal to zero.

CMEQ Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Compare bitwise equal to zero.

CMEQ Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Compare bitwise equal to zero.

CMEQ Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Compare bitwise equal to zero.

CMEQ Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Compare bitwise equal to zero.

CMEQ Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Compare bitwise equal to zero.

CMEQ Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Compare bitwise equal to zero.

CMEQ Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Compare bitwise equal to zero.

CMEQ Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Compare bitwise equal to zero.

CMEQ Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point compare equal to zero.

FCMEQ Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point compare equal to zero.

FCMEQ Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Compare bitwise equal to zero.

CMEQ Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Compare bitwise equal to zero.

CMEQ Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Compare bitwise equal to zero.

CMEQ Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare bitwise equal to zero.

CMEQ Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Compare bitwise equal to zero.

CMEQ Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare bitwise equal to zero.

CMEQ Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Compare bitwise equal to zero.

CMEQ Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A32/A64

Compare bitwise equal to zero.

CMEQ Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A32/A64

Floating-point compare equal to zero.

FCMEQ Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point compare equal to zero.

FCMEQ Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Compare bitwise equal to zero.

CMEQ Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare bitwise equal to zero.

CMEQ Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point compare equal to zero.

FCMEQ Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Floating-point compare equal to zero.

FCMEQ Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare bitwise equal to zero.

CMEQ Vd.8B,Vn.8B,#0

a → Vn.8B

Vd.8B → result

A64

Compare bitwise equal to zero.

CMEQ Vd.16B,Vn.16B,#0

a → Vn.16B

Vd.16B → result

A64

Compare bitwise equal to zero.

CMEQ Vd.4H,Vn.4H,#0

a → Vn.4H

Vd.4H → result

A64

Compare bitwise equal to zero.

CMEQ Vd.8H,Vn.8H,#0

a → Vn.8H

Vd.8H → result

A64

Compare bitwise equal to zero.

CMEQ Vd.2S,Vn.2S,#0

a → Vn.2S

Vd.2S → result

A64

Compare bitwise equal to zero.

CMEQ Vd.4S,Vn.4S,#0

a → Vn.4S

Vd.4S → result

A64

Compare bitwise equal to zero.

CMEQ Vd.8B,Vn.8B,#0

a → Vn.8B

Vd.8B → result

A64

Compare bitwise equal to zero.

CMEQ Vd.16B,Vn.16B,#0

a → Vn.16B

Vd.16B → result

A64

Compare bitwise equal to zero.

CMEQ Vd.4H,Vn.4H,#0

a → Vn.4H

Vd.4H → result

A64

Compare bitwise equal to zero.

CMEQ Vd.8H,Vn.8H,#0

a → Vn.8H

Vd.8H → result

A64

Compare bitwise equal to zero.

CMEQ Vd.2S,Vn.2S,#0

a → Vn.2S

Vd.2S → result

A64

Compare bitwise equal to zero.

CMEQ Vd.4S,Vn.4S,#0

a → Vn.4S

Vd.4S → result

A64

Floating-point compare equal to zero.

FCMEQ Vd.2S,Vn.2S,#0

a → Vn.2S

Vd.2S → result

A64

Floating-point compare equal to zero.

FCMEQ Vd.4S,Vn.4S,#0

a → Vn.4S

Vd.4S → result

A64

Compare bitwise equal to zero.

CMEQ Vd.8B,Vn.8B,#0

a → Vn.8B

Vd.8B → result

A64

Compare bitwise equal to zero.

CMEQ Vd.16B,Vn.16B,#0

a → Vn.16B

Vd.16B → result

A64

Compare bitwise equal to zero.

CMEQ Dd,Dn,#0

a → Dn

Dd → result

A64

Compare bitwise equal to zero.

CMEQ Vd.2D,Vn.2D,#0

a → Vn.2D

Vd.2D → result

A64

Compare bitwise equal to zero.

CMEQ Dd,Dn,#0

a → Dn

Dd → result

A64

Compare bitwise equal to zero.

CMEQ Vd.2D,Vn.2D,#0

a → Vn.2D

Vd.2D → result

A64

Compare bitwise equal to zero.

CMEQ Dd,Dn,#0

a → Dn

Dd → result

A32/A64

Compare bitwise equal to zero.

CMEQ Vd.2D,Vn.2D,#0

a → Vn.2D

Vd.2D → result

A32/A64

Floating-point compare equal to zero.

FCMEQ Dd,Dn,#0

a → Dn

Dd → result

A64

Floating-point compare equal to zero.

FCMEQ Vd.2D,Vn.2D,#0

a → Vn.2D

Vd.2D → result

A64

Compare bitwise equal to zero.

CMEQ Dd,Dn,#0

a → Dn

Dd → result

A64

Compare bitwise equal to zero.

CMEQ Dd,Dn,#0

a → Dn

Dd → result

A64

Floating-point compare equal to zero.

FCMEQ Sd,Sn,#0

a → Sn

Sd → result

A64

Floating-point compare equal to zero.

FCMEQ Dd,Dn,#0

a → Dn

Dd → result

A64

Compare signed greater than or equal to zero.

CMGE Vd.8B,Vm.8B,Vn.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Compare signed greater than or equal to zero.

CMGE Vd.16B,Vm.16B,Vn.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Compare signed greater than or equal to zero.

CMGE Vd.4H,Vm.4H,Vn.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Compare signed greater than or equal to zero.

CMGE Vd.8H,Vm.8H,Vn.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Compare signed greater than or equal to zero.

CMGE Vd.2S,Vm.2S,Vn.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Compare signed greater than or equal to zero.

CMGE Vd.4S,Vm.4S,Vn.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Compare unsigned higher or same.

CMHS Vd.8B,Vm.8B,Vn.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Compare unsigned higher or same.

CMHS Vd.16B,Vm.16B,Vn.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Compare unsigned higher or same.

CMHS Vd.4H,Vm.4H,Vn.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Compare unsigned higher or same.

CMHS Vd.8H,Vm.8H,Vn.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Compare unsigned higher or same.

CMHS Vd.2S,Vm.2S,Vn.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Compare unsigned higher or same.

CMHS Vd.4S,Vm.4S,Vn.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point compare greater than or equal to zero.

FCMGE Vd.2S,Vm.2S,Vn.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point compare greater than or equal to zero.

FCMGE Vd.4S,Vm.4S,Vn.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Compare signed greater than or equal to zero.

CMGE Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare signed greater than or equal to zero.

CMGE Vd.2D,Vm.2D,Vn.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Compare unsigned higher or same.

CMHS Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare unsigned higher or same.

CMHS Vd.2D,Vm.2D,Vn.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Floating-point compare greater than or equal to zero.

FCMGE Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point compare greater than or equal to zero.

FCMGE Vd.2D,Vm.2D,Vn.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Compare signed greater than or equal to zero.

CMGE Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare unsigned higher or same.

CMHS Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point compare greater than or equal to zero.

FCMGE Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Floating-point compare greater than or equal to zero.

FCMGE Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare signed greater than or equal to zero.

CMGE Vd.8B,Vn.8B,#0

a → Vn.8B

Vd.8B → result

A64

Compare signed greater than or equal to zero.

CMGE Vd.16B,Vn.16B,#0

a → Vn.16B

Vd.16B → result

A64

Compare signed greater than or equal to zero.

CMGE Vd.4H,Vn.4H,#0

a → Vn.4H

Vd.4H → result

A64

Compare signed greater than or equal to zero.

CMGE Vd.8H,Vn.8H,#0

a → Vn.8H

Vd.8H → result

A64

Compare signed greater than or equal to zero.

CMGE Vd.2S,Vn.2S,#0

a → Vn.2S

Vd.2S → result

A64

Compare signed greater than or equal to zero.

CMGE Vd.4S,Vn.4S,#0

a → Vn.4S

Vd.4S → result

A64

Compare signed greater than or equal to zero.

CMGE Dd,Dn,#0

a → Dn

Dd → result

A64

Compare signed greater than or equal to zero.

CMGE Vd.2D,Vn.2D,#0

a → Vn.2D

Vd.2D → result

A64

Floating-point compare greater than or equal to zero.

FCMGE Vd.2S,Vn.2S,#0

a → Vn.2S

Vd.2S → result

A64

Floating-point compare greater than or equal to zero.

FCMGE Vd.4S,Vn.4S,#0

a → Vn.4S

Vd.4S → result

A64

Floating-point compare greater than or equal to zero.

FCMGE Dd,Dn,#0

a → Dn

Dd → result

A64

Floating-point compare greater than or equal to zero.

FCMGE Vd.2D,Vn.2D,#0

a → Vn.2D

Vd.2D → result

A64

Compare signed greater than or equal to zero.

CMGE Dd,Dn,#0

a → Dn

Dd → result

A64

Floating-point compare greater than or equal to zero.

FCMGE Sd,Sn,#0

a → Sn

Sd → result

A64

Floating-point compare greater than or equal to zero.

FCMGE Dd,Dn,#0

a → Dn

Dd → result

A64

Compare signed greater than or equal to zero.

CMGE Vd.8B,Vm.8B,Vn.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Compare signed greater than or equal to zero.

CMGE Vd.16B,Vm.16B,Vn.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Compare signed greater than or equal to zero.

CMGE Vd.4H,Vm.4H,Vn.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Compare signed greater than or equal to zero.

CMGE Vd.8H,Vm.8H,Vn.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Compare signed greater than or equal to zero.

CMGE Vd.2S,Vm.2S,Vn.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Compare signed greater than or equal to zero.

CMGE Vd.4S,Vm.4S,Vn.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Compare unsigned higher or same.

CMHS Vd.8B,Vm.8B,Vn.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Compare unsigned higher or same.

CMHS Vd.16B,Vm.16B,Vn.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Compare unsigned higher or same.

CMHS Vd.4H,Vm.4H,Vn.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Compare unsigned higher or same.

CMHS Vd.8H,Vm.8H,Vn.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Compare unsigned higher or same.

CMHS Vd.2S,Vm.2S,Vn.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Compare unsigned higher or same.

CMHS Vd.4S,Vm.4S,Vn.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point compare greater than or equal to zero.

FCMGE Vd.2S,Vm.2S,Vn.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point compare greater than or equal to zero.

FCMGE Vd.4S,Vm.4S,Vn.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Compare signed greater than or equal to zero.

CMGE Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Compare signed greater than or equal to zero.

CMGE Vd.2D,Vm.2D,Vn.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Compare unsigned higher or same.

CMHS Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Compare unsigned higher or same.

CMHS Vd.2D,Vm.2D,Vn.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Floating-point compare greater than or equal to zero.

FCMGE Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Floating-point compare greater than or equal to zero.

FCMGE Vd.2D,Vm.2D,Vn.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Compare signed greater than or equal to zero.

CMGE Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Compare unsigned higher or same.

CMHS Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Floating-point compare greater than or equal to zero.

FCMGE Sd,Sm,Sn

a → Sn

b → Sm

Sd → result

A64

Floating-point compare greater than or equal to zero.

FCMGE Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Compare signed less than or equal to zero.

CMLE Vd.8B,Vn.8B,#0

a → Vn.8B

Vd.8B → result

A64

Compare signed less than or equal to zero.

CMLE Vd.16B,Vn.16B,#0

a → Vn.16B

Vd.16B → result

A64

Compare signed less than or equal to zero.

CMLE Vd.4H,Vn.4H,#0

a → Vn.4H

Vd.4H → result

A64

Compare signed less than or equal to zero.

CMLE Vd.8H,Vn.8H,#0

a → Vn.8H

Vd.8H → result

A64

Compare signed less than or equal to zero.

CMLE Vd.2S,Vn.2S,#0

a → Vn.2S

Vd.2S → result

A64

Compare signed less than or equal to zero.

CMLE Vd.4S,Vn.4S,#0

a → Vn.4S

Vd.4S → result

A64

Compare signed less than or equal to zero.

CMLE Dd,Dn,#0

a → Dn

Dd → result

A64

Compare signed less than or equal to zero.

CMLE Vd.2D,Vn.2D,#0

a → Vn.2D

Vd.2D → result

A64

Compare signed less than or equal to zero.

CMLE Vd.2S,Vn.2S,#0

a → Vn.2S

Vd.2S → result

A64

Floating-point compare less than or equal to zero.

FCMLE Vd.4S,Vn.4S,#0

a → Vn.4S

Vd.4S → result

A64

Floating-point compare less than or equal to zero.

FCMLE Dd,Dn,#0

a → Dn

Dd → result

A64

Floating-point compare less than or equal to zero.

FCMLE Vd.2D,Vn.2D,#0

a → Vn.2D

Vd.2D → result

A64

Compare signed less than or equal to zero.

CMLE Dd,Dn,#0

a → Dn

Dd → result

A64

Floating-point compare less than or equal to zero.

FCMLE Sd,Sn,#0

a → Sn

Sd → result

A64

Floating-point compare less than or equal to zero.

FCMLE Dd,Dn,#0

a → Dn

Dd → result

A64

Compare signed greater than zero.

CMGT Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Compare signed greater than zero.

CMGT Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Compare signed greater than zero.

CMGT Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Compare signed greater than zero.

CMGT Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Compare signed greater than zero.

CMGT Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Compare signed greater than zero.

CMGT Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Compare unsigned higher.

CMHI Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Compare unsigned higher.

CMHI Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Compare unsigned higher.

CMHI Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Compare unsigned higher.

CMHI Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Compare unsigned higher.

CMHI Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Compare unsigned higher.

CMHI Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point compare greater than zero.

FCMGT Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point compare greater than zero.

FCMGT Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Compare signed greater than zero.

CMGT Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare signed greater than zero.

CMGT Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Compare unsigned higher.

CMHI Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare unsigned higher.

CMHI Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Floating-point compare greater than zero.

FCMGT Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point compare greater than zero.

FCMGT Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Compare signed greater than zero.

CMGT Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare unsigned higher.

CMHI Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point compare greater than zero.

FCMGT Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Floating-point compare greater than zero.

FCMGT Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare signed greater than zero.

CMGT Vd.8B,Vn.8B,#0

a → Vn.8B

Vd.8B → result

A64

Compare signed greater than zero.

CMGT Vd.16B,Vn.16B,#0

a → Vn.16B

Vd.16B → result

A64

Compare signed greater than zero.

CMGT Vd.4H,Vn.4H,#0

a → Vn.4H

Vd.4H → result

A64

Compare signed greater than zero.

CMGT Vd.8H,Vn.8H,#0

a → Vn.8H

Vd.8H → result

A64

Compare signed greater than zero.

CMGT Vd.2S,Vn.2S,#0

a → Vn.2S

Vd.2S → result

A64

Compare signed greater than zero.

CMGT Vd.4S,Vn.4S,#0

a → Vn.4S

Vd.4S → result

A64

Compare signed greater than zero.

CMGT Dd,Dn,#0

a → Dn

Dd → result

A64

Compare signed greater than zero.

CMGT Vd.2D,Vn.2D,#0

a → Vn.2D

Vd.2D → result

A64

Floating-point compare greater than zero.

FCMGT Vd.2S,Vn.2S,#0

a → Vn.2S

Vd.2S → result

A64

Floating-point compare greater than zero.

FCMGT Vd.4S,Vn.4S,#0

a → Vn.4S

Vd.4S → result

A64

Floating-point compare greater than zero.

FCMGT Dd,Dn,#0

a → Dn

Dd → result

A64

Floating-point compare greater than zero.

FCMGT Vd.2D,Vn.2D,#0

a → Vn.2D

Vd.2D → result

A64

Compare signed greater than zero.

CMGT Dd,Dn,#0

a → Dn

Dd → result

A64

Floating-point compare greater than zero.

FCMGT Sd,Sn,#0

a → Sn

Sd → result

A64

Floating-point compare greater than zero.

FCMGT Dd,Dn,#0

a → Dn

Dd → result

A64

Compare signed greater than zero.

CMGT Vd.8B,Vm.8B,Vn.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Compare signed greater than zero.

CMGT Vd.16B,Vm.16B,Vn.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Compare signed greater than zero.

CMGT Vd.4H,Vm.4H,Vn.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Compare signed greater than zero.

CMGT Vd.8H,Vm.8H,Vn.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Compare signed greater than zero.

CMGT Vd.2S,Vm.2S,Vn.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Compare signed greater than zero.

CMGT Vd.4S,Vm.4S,Vn.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Compare unsigned higher.

CMHI Vd.8B,Vm.8B,Vn.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Compare unsigned higher.

CMHI Vd.16B,Vm.16B,Vn.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Compare unsigned higher.

CMHI Vd.4H,Vm.4H,Vn.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Compare unsigned higher.

CMHI Vd.8H,Vm.8H,Vn.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Compare unsigned higher.

CMHI Vd.2S,Vm.2S,Vn.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Compare unsigned higher.

CMHI Vd.4S,Vm.4S,Vn.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point compare greater than zero.

FCMGT Vd.2S,Vm.2S,Vn.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point compare greater than zero.

FCMGT Vd.4S,Vm.4S,Vn.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Compare signed greater than zero.

CMGT Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Compare signed greater than zero.

CMGT Vd.2D,Vm.2D,Vn.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Compare unsigned higher.

CMHI Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Compare unsigned higher.

CMHI Vd.2D,Vm.2D,Vn.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Floating-point compare greater than zero.

FCMGT Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Floating-point compare greater than zero.

FCMGT Vd.2D,Vm.2D,Vn.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Compare signed greater than zero.

CMGT Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Compare unsigned higher.

CMHI Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Floating-point compare greater than zero.

FCMGT Sd,Sm,Sn

a → Sn

b → Sm

Sd → result

A64

Floating-point compare greater than zero.

FCMGT Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Compare signed less than zero.

CMLT Vd.8B,Vn.8B,#0

a → Vn.8B

Vd.8B → result

A64

Compare signed less than zero.

CMLT Vd.16B,Vn.16B,#0

a → Vn.16B

Vd.16B → result

A64

Compare signed less than zero.

CMLT Vd.4H,Vn.4H,#0

a → Vn.4H

Vd.4H → result

A64

Compare signed less than zero.

CMLT Vd.8H,Vn.8H,#0

a → Vn.8H

Vd.8H → result

A64

Compare signed less than zero.

CMLT Vd.2S,Vn.2S,#0

a → Vn.2S

Vd.2S → result

A64

Compare signed less than zero.

CMLT Vd.4S,Vn.4S,#0

a → Vn.4S

Vd.4S → result

A64

Compare signed less than zero.

CMLT Dd,Dn,#0

a → Dn

Dd → result

A64

Compare signed less than zero.

CMLT Vd.2D,Vn.2D,#0

a → Vn.2D

Vd.2D → result

A64

Floating-point compare less than zero.

FCMLT Vd.2S,Vn.2S,#0

a → Vn.2S

Vd.2S → result

A64

Floating-point compare less than zero.

FCMLT Vd.4S,Vn.4S,#0

a → Vn.4S

Vd.4S → result

A64

Floating-point compare less than zero.

FCMLT Dd,Dn,#0

a → Dn

Dd → result

A64

Floating-point compare less than zero.

FCMLT Vd.2D,Vn.2D,#0

a → Vn.2D

Vd.2D → result

A64

Compare signed less than zero.

CMLT Dd,Dn,#0

a → Dn

Dd → result

A64

Floating-point compare less than zero.

FCMLT Sd,Sn,#0

a → Sn

Sd → result

A64

Floating-point compare less than zero.

FCMLT Dd,Dn,#0

a → Dn

Dd → result

A64

Floating-point absolute compare greater than or equal.

FACGE Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point absolute compare greater than or equal.

FACGE Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point absolute compare greater than or equal.

FACGE Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point absolute compare greater than or equal.

FACGE Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Floating-point absolute compare greater than or equal.

FACGE Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Floating-point absolute compare greater than or equal.

FACGE Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point absolute compare greater than or equal.

FACGE Vd.2S,Vm.2S,Vn.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point absolute compare greater than or equal.

FACGE Vd.4S,Vm.4S,Vn.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point absolute compare greater than or equal.

FACGE Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Floating-point absolute compare greater than or equal.

FACGE Vd.2D,Vm.2D,Vn.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Floating-point absolute compare greater than or equal.

FACGE Sd,Sm,Sn

a → Sn

b → Sm

Sd → result

A64

Floating-point absolute compare greater than or equal.

FACGE Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Floating-point absolute compare greater than.

FACGT Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point absolute compare greater than.

FACGT Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point absolute compare greater than.

FACGT Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point absolute compare greater than.

FACGT Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Floating-point absolute compare greater than.

FACGT Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Floating-point absolute compare greater than.

FACGT Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point absolute compare greater than.

FACGT Vd.2S,Vm.2S,Vn.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point absolute compare greater than.

FACGT Vd.4S,Vm.4S,Vn.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point absolute compare greater than.

FACGT Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Floating-point absolute compare greater than.

FACGT Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Floating-point absolute compare greater than.

FACGT Sd,Sm,Sn

a → Sn

b → Sm

Sd → result

A64

Floating-point absolute compare greater than.

FACGT Dd,Dm,Dn

a → Dn

b → Dm

Dd → result

A64

Compare bitwise test bits nonzero.

CMTST Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Compare bitwise test bits nonzero.

CMTST Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Compare bitwise test bits nonzero.

CMTST Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Compare bitwise test bits nonzero.

CMTST Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Compare bitwise test bits nonzero.

CMTST Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Compare bitwise test bits nonzero.

CMTST Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Compare bitwise test bits nonzero.

CMTST Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Compare bitwise test bits nonzero.

CMTST Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Compare bitwise test bits nonzero.

CMTST Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Compare bitwise test bits nonzero.

CMTST Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Compare bitwise test bits nonzero.

CMTST Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Compare bitwise test bits nonzero.

CMTST Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Compare bitwise test bits nonzero.

CMTST Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Compare bitwise test bits nonzero.

CMTST Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Compare bitwise test bits nonzero.

CMTST Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare bitwise test bits nonzero.

CMTST Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Compare bitwise test bits nonzero.

CMTST Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare bitwise test bits nonzero.

CMTST Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Compare bitwise test bits nonzero.

CMTST Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A32/A64

Compare bitwise test bits nonzero.

CMTST Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A32/A64

Compare bitwise test bits nonzero.

CMTST Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Compare bitwise test bits nonzero.

CMTST Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Signed absolute difference.

SABD Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Signed absolute difference.

SABD Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Signed absolute difference.

SABD Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Signed absolute difference.

SABD Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Signed absolute difference.

SABD Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Signed absolute difference.

SABD Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Unsigned absolute difference.

UABD Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Unsigned absolute difference.

UABD Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Unsigned absolute difference.

UABD Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Unsigned absolute difference.

UABD Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Unsigned absolute difference.

UABD Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Unsigned absolute difference.

UABD Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point absolute difference.

FABD Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point absolute difference.

FABD Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point absolute difference.

FABD Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point absolute difference.

FABD Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Floating-point absolute difference.

FABD Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Floating-point absolute difference.

FABD Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Signed absolute difference long.

SABDL Vd.8H,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8H → result

v7/A32/A64

Signed absolute difference long.

SABDL Vd.4S,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4S → result

v7/A32/A64

Signed absolute difference long.

SABDL Vd.2D,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2D → result

v7/A32/A64

Unsigned absolute difference long.

UABDL Vd.8H,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8H → result

v7/A32/A64

Unsigned absolute difference long.

UABDL Vd.4S,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4S → result

v7/A32/A64

Unsigned absolute difference long.

UABDL Vd.2D,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2D → result

v7/A32/A64

Signed absolute difference long.

SABDL2 Vd.8H,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.8H → result

A64

Signed absolute difference long.

SABDL2 Vd.4S,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.4S → result

A64

Signed absolute difference long.

SABDL2 Vd.2D,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.2D → result

A64

Unsigned absolute difference long.

UABDL2 Vd.8H,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.8H → result

A64

Unsigned absolute difference long.

UABDL2 Vd.4S,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.4S → result

A64

Unsigned absolute difference long.

UABDL2 Vd.2D,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.2D → result

A64

Signed absolute difference and accumulate.

SABA Vd.8B,Vn.8B,Vm.8B

a → Vd.8B

b → Vn.8B

c → Vm.8B

Vd.8B → result

v7/A32/A64

Signed absolute difference and accumulate.

SABA Vd.16B,Vn.16B,Vm.16B

a → Vd.16B

b → Vn.16B

c → Vm.16B

Vd.16B → result

v7/A32/A64

Signed absolute difference and accumulate.

SABA Vd.4H,Vn.4H,Vm.4H

a → Vd.4H

b → Vn.4H

c → Vm.4H

Vd.4H → result

v7/A32/A64

Signed absolute difference and accumulate.

SABA Vd.8H,Vn.8H,Vm.8H

a → Vd.8H

b → Vn.8H

c → Vm.8H

Vd.8H → result

v7/A32/A64

Signed absolute difference and accumulate.

SABA Vd.2S,Vn.2S,Vm.2S

a → Vd.2S

b → Vn.2S

c → Vm.2S

Vd.2S → result

v7/A32/A64

Signed absolute difference and accumulate.

SABA Vd.4S,Vn.4S,Vm.4S

a → Vd.4S

b → Vn.4S

c → Vm.4S

Vd.4S → result

v7/A32/A64

Unsigned absolute difference and accumulate.

UABA Vd.8B,Vn.8B,Vm.8B

a → Vd.8B

b → Vn.8B

c → Vm.8B

Vd.8B → result

v7/A32/A64

Unsigned absolute difference and accumulate.

UABA Vd.16B,Vn.16B,Vm.16B

a → Vd.16B

b → Vn.16B

c → Vm.16B

Vd.16B → result

v7/A32/A64

Unsigned absolute difference and accumulate.

UABA Vd.4H,Vn.4H,Vm.4H

a → Vd.4H

b → Vn.4H

c → Vm.4H

Vd.4H → result

v7/A32/A64

Unsigned absolute difference and accumulate.

UABA Vd.8H,Vn.8H,Vm.8H

a → Vd.8H

b → Vn.8H

c → Vm.8H

Vd.8H → result

v7/A32/A64

Unsigned absolute difference and accumulate.

UABA Vd.2S,Vn.2S,Vm.2S

a → Vd.2S

b → Vn.2S

c → Vm.2S

Vd.2S → result

v7/A32/A64

Unsigned absolute difference and accumulate.

UABA Vd.4S,Vn.4S,Vm.4S

a → Vd.4S

b → Vn.4S

c → Vm.4S

Vd.4S → result

v7/A32/A64

Signed absolute difference and accumulate long.

SABAL Vd.8H,Vn.8B,Vm.8B

a → Vd.8H

b → Vn.8B

c → Vm.8B

Vd.8H → result

v7/A32/A64

Signed absolute difference and accumulate long.

SABAL Vd.4S,Vn.4H,Vm.4H

a → Vd.4S

b → Vn.4H

c → Vm.4H

Vd.4S → result

v7/A32/A64

Signed absolute difference and accumulate long.

SABAL Vd.2D,Vn.2S,Vm.2S

a → Vd.2D

b → Vn.2S

c → Vm.2S

Vd.2D → result

v7/A32/A64

Unsigned absolute difference and accumulate long.

UABAL Vd.8H,Vn.8B,Vm.8B

a → Vd.8H

b → Vn.8B

c → Vm.8B

Vd.8H → result

v7/A32/A64

Unsigned absolute difference and accumulate long.

UABAL Vd.4S,Vn.4H,Vm.4H

a → Vd.4S

b → Vn.4H

c → Vm.4H

Vd.4S → result

v7/A32/A64

Unsigned absolute difference and accumulate long.

UABAL Vd.2D,Vn.2S,Vm.2S

a → Vd.2D

b → Vn.2S

c → Vm.2S

Vd.2D → result

v7/A32/A64

Signed absolute difference and accumulate long.

SABAL2 Vd.8H,Vn.16B,Vm.16B

a → Vd.8H

b → Vn.16B

c → Vm.16B

Vd.8H → result

A64

Signed absolute difference and accumulate long.

SABAL2 Vd.4S,Vn.8H,Vm.8H

a → Vd.4S

b → Vn.8H

c → Vm.8H

Vd.4S → result

A64

Signed absolute difference and accumulate long.

SABAL2 Vd.2D,Vn.4S,Vm.4S

a → Vd.2D

b → Vn.4S

c → Vm.4S

Vd.2D → result

A64

Unsigned absolute difference and accumulate long.

UABAL2 Vd.8H,Vn.16B,Vm.16B

a → Vd.8H

b → Vn.16B

c → Vm.16B

Vd.8H → result

A64

Unsigned absolute difference and accumulate long.

UABAL2 Vd.4S,Vn.8H,Vm.8H

a → Vd.4S

b → Vn.8H

c → Vm.8H

Vd.4S → result

A64

Unsigned absolute difference and accumulate long.

UABAL2 Vd.2D,Vn.4S,Vm.4S

a → Vd.2D

b → Vn.4S

c → Vm.4S

Vd.2D → result

A64

Signed maximum.

SMAX Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Signed maximum.

SMAX Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Signed maximum.

SMAX Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Signed maximum.

SMAX Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Signed maximum.

SMAX Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Signed maximum.

SMAX Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Unsigned maximum.

UMAX Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Unsigned maximum.

UMAX Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Unsigned maximum.

UMAX Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Unsigned maximum.

UMAX Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Unsigned maximum.

UMAX Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Unsigned maximum.

UMAX Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point maximum.

FMAX Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point maximum.

FMAX Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point maximum.

FMAX Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point maximum.

FMAX Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Signed minimum.

SMIN Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Signed minimum.

SMIN Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Signed minimum.

SMIN Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Signed minimum.

SMIN Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Signed minimum.

SMIN Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Signed minimum.

SMIN Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Unsigned minimum.

UMIN Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Unsigned minimum.

UMIN Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Unsigned minimum.

UMIN Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Unsigned minimum.

UMIN Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Unsigned minimum.

UMIN Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Unsigned minimum.

UMIN Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point minimum.

FMIN Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Floating-point minimum.

FMIN Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Floating-point minimum.

FMIN Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point minimum.

FMIN Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Floating-point maximum number.

FMAXNM Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

A32/A64

Floating-point maximum number.

FMAXNM Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

A32/A64

Floating-point maximum number.

FMAXNM Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point maximum number.

FMAXNM Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Floating-point minimum number.

FMINNM Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

A32/A64

Floating-point minimum number.

FMINNM Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

A32/A64

Floating-point minimum number.

FMINNM Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Floating-point minimum number.

FMINNM Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

A64

Signed shift left.

SSHL Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Signed shift left.

SSHL Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Signed shift left.

SSHL Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Signed shift left.

SSHL Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Signed shift left.

SSHL Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Signed shift left.

SSHL Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Signed shift left.

SSHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Signed shift left.

SSHL Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Unsigned shift left.

USHL Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Unsigned shift left.

USHL Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Unsigned shift left.

USHL Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Unsigned shift left.

USHL Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Unsigned shift left.

USHL Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Unsigned shift left.

USHL Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Unsigned shift left.

USHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Unsigned shift left.

USHL Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Signed shift left.

SSHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Unsigned shift left.

USHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Signed saturating shift left.

SQSHL Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Signed saturating shift left.

SQSHL Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Signed saturating shift left.

SQSHL Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Signed saturating shift left.

SQSHL Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Signed saturating shift left.

SQSHL Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Signed saturating shift left.

SQSHL Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Signed saturating shift left.

SQSHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Signed saturating shift left.

SQSHL Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Signed saturating shift left.

SQSHL Bd,Bn,Bm

a → Bn

b → Bm

Bd → result

A64

Signed saturating shift left.

SQSHL Hd,Hn,Hm

a → Hn

b → Hm

Hd → result

A64

Signed saturating shift left.

SQSHL Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Signed saturating shift left.

SQSHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Unsigned saturating shift left.

UQSHL Bd,Bn,Bm

a → Bn

b → Bm

Bd → result

A64

Unsigned saturating shift left.

UQSHL Hd,Hn,Hm

a → Hn

b → Hm

Hd → result

A64

Unsigned saturating shift left.

UQSHL Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Unsigned saturating shift left.

UQSHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Signed rounding shift left.

SRSHL Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Signed rounding shift left.

SRSHL Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Signed rounding shift left.

SRSHL Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Signed rounding shift left.

SRSHL Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Signed rounding shift left.

SRSHL Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Signed rounding shift left.

SRSHL Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Signed rounding shift left.

SRSHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Signed rounding shift left.

SRSHL Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Unsigned rounding shift left.

URSHL Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Unsigned rounding shift left.

URSHL Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Unsigned rounding shift left.

URSHL Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Unsigned rounding shift left.

URSHL Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Unsigned rounding shift left.

URSHL Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Unsigned rounding shift left.

URSHL Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Unsigned rounding shift left.

URSHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Unsigned rounding shift left.

URSHL Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Signed rounding shift left.

SRSHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Unsigned rounding shift left.

URSHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Signed saturating rounding shift left.

SQRSHL Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Signed saturating rounding shift left.

SQRSHL Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Signed saturating rounding shift left.

SQRSHL Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Signed saturating rounding shift left.

SQRSHL Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Signed saturating rounding shift left.

SQRSHL Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Signed saturating rounding shift left.

SQRSHL Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Signed saturating rounding shift left.

SQRSHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Signed saturating rounding shift left.

SQRSHL Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Unsigned saturating rounding shift left.

UQRSHL Vd.8B,Vn.8B,Vm.8B

a → Vn.8B

b → Vm.8B

Vd.8B → result

v7/A32/A64

Unsigned saturating rounding shift left.

UQRSHL Vd.16B,Vn.16B,Vm.16B

a → Vn.16B

b → Vm.16B

Vd.16B → result

v7/A32/A64

Unsigned saturating rounding shift left.

UQRSHL Vd.4H,Vn.4H,Vm.4H

a → Vn.4H

b → Vm.4H

Vd.4H → result

v7/A32/A64

Unsigned saturating rounding shift left.

UQRSHL Vd.8H,Vn.8H,Vm.8H

a → Vn.8H

b → Vm.8H

Vd.8H → result

v7/A32/A64

Unsigned saturating rounding shift left.

UQRSHL Vd.2S,Vn.2S,Vm.2S

a → Vn.2S

b → Vm.2S

Vd.2S → result

v7/A32/A64

Unsigned saturating rounding shift left.

UQRSHL Vd.4S,Vn.4S,Vm.4S

a → Vn.4S

b → Vm.4S

Vd.4S → result

v7/A32/A64

Unsigned saturating rounding shift left.

UQRSHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

v7/A32/A64

Unsigned saturating rounding shift left.

UQRSHL Vd.2D,Vn.2D,Vm.2D

a → Vn.2D

b → Vm.2D

Vd.2D → result

v7/A32/A64

Signed saturating rounding shift left.

SQRSHL Bd,Bn,Bm

a → Bn

b → Bm

Bd → result

A64

Signed saturating rounding shift left.

SQRSHL Hd,Hn,Hm

a → Hn

b → Hm

Hd → result

A64

Signed saturating rounding shift left.

SQRSHL Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Signed saturating rounding shift left.

SQRSHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Unsigned saturating rounding shift left.

UQRSHL Bd,Bn,Bm

a → Bn

b → Bm

Bd → result

A64

Unsigned saturating rounding shift left.

UQRSHL Hd,Hn,Hm

a → Hn

b → Hm

Hd → result

A64

Unsigned saturating rounding shift left.

UQRSHL Sd,Sn,Sm

a → Sn

b → Sm

Sd → result

A64

Unsigned saturating rounding shift left.

UQRSHL Dd,Dn,Dm

a → Dn

b → Dm

Dd → result

A64

Signed shift right.

SSHR Vd.8B,Vn.8B,#n

a → Vn.8B

1 << n << 8

Vd.8B → result

v7/A32/A64

Signed shift right.

SSHR Vd.16B,Vn.16B,#n

a → Vn.16B

1 << n << 8

Vd.16B → result

v7/A32/A64

Signed shift right.

SSHR Vd.4H,Vn.4H,#n

a → Vn.4H

1 << n << 16

Vd.4H → result

v7/A32/A64

Signed shift right.

SSHR Vd.8H,Vn.8H,#n

a → Vn.8H

1 << n << 16

Vd.8H → result

v7/A32/A64

Signed shift right.

SSHR Vd.2S,Vn.2S,#n

a → Vn.2S

1 << n << 32

Vd.2S → result

v7/A32/A64

Signed shift right.

SSHR Vd.4S,Vn.4S,#n

a → Vn.4S

1 << n << 32

Vd.4S → result

v7/A32/A64

Signed shift right.

SSHR Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

v7/A32/A64

Signed shift right.

SSHR Vd.2D,Vn.2D,#n

a → Vn.2D

1 << n << 64

Vd.2D → result

v7/A32/A64

Unsigned shift right.

USHR Vd.8B,Vn.8B,#n

a → Vn.8B

1 << n << 8

Vd.8B → result

v7/A32/A64

Unsigned shift right.

USHR Vd.16B,Vn.16B,#n

a → Vn.16B

1 << n << 8

Vd.16B → result

v7/A32/A64

Unsigned shift right.

USHR Vd.4H,Vn.4H,#n

a → Vn.4H

1 << n << 16

Vd.4H → result

v7/A32/A64

Unsigned shift right.

USHR Vd.8H,Vn.8H,#n

a → Vn.8H

1 << n << 16

Vd.8H → result

v7/A32/A64

Unsigned shift right.

USHR Vd.2S,Vn.2S,#n

a → Vn.2S

1 << n << 32

Vd.2S → result

v7/A32/A64

Unsigned shift right.

USHR Vd.4S,Vn.4S,#n

a → Vn.4S

1 << n << 32

Vd.4S → result

v7/A32/A64

Unsigned shift right.

USHR Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

v7/A32/A64

Unsigned shift right.

USHR Vd.2D,Vn.2D,#n

a → Vn.2D

1 << n << 64

Vd.2D → result

v7/A32/A64

Signed shift right.

SSHR Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

A64

Unsigned shift right.

USHR Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

A64

Shift left.

SHL Vd.8B,Vn.8B,#n

a → Vn.8B

0 << n << 7

Vd.8B → result

v7/A32/A64

Shift left.

SHL Vd.16B,Vn.16B,#n

a → Vn.16B

0 << n << 7

Vd.16B → result

v7/A32/A64

Shift left.

SHL Vd.4H,Vn.4H,#n

a → Vn.4H

0 << n << 15

Vd.4H → result

v7/A32/A64

Shift left.

SHL Vd.8H,Vn.8H,#n

a → Vn.8H

0 << n << 15

Vd.8H → result

v7/A32/A64

Shift left.

SHL Vd.2S,Vn.2S,#n

a → Vn.2S

0 << n << 31

Vd.2S → result

v7/A32/A64

Shift left.

SHL Vd.4S,Vn.4S,#n

a → Vn.4S

0 << n << 31

Vd.4S → result

v7/A32/A64

Shift left.

SHL Dd,Dn,#n

a → Dn

0 << n << 63

Dd → result

v7/A32/A64

Shift left.

SHL Vd.2D,Vn.2D,#n

a → Vn.2D

0 << n << 63

Vd.2D → result

v7/A32/A64

Shift left.

SHL Vd.8B,Vn.8B,#n

a → Vn.8B

0 << n << 7

Vd.8B → result

v7/A32/A64

Shift left.

SHL Vd.16B,Vn.16B,#n

a → Vn.16B

0 << n << 7

Vd.16B → result

v7/A32/A64

Shift left.

SHL Vd.4H,Vn.4H,#n

a → Vn.4H

0 << n << 15

Vd.4H → result

v7/A32/A64

Shift left.

SHL Vd.8H,Vn.8H,#n

a → Vn.8H

0 << n << 15

Vd.8H → result

v7/A32/A64

Shift left.

SHL Vd.2S,Vn.2S,#n

a → Vn.2S

0 << n << 31

Vd.2S → result

v7/A32/A64

Shift left.

SHL Vd.4S,Vn.4S,#n

a → Vn.4S

0 << n << 31

Vd.4S → result

v7/A32/A64

Shift left.

SHL Dd,Dn,#n

a → Dn

0 << n << 63

Dd → result

v7/A32/A64

Shift left.

SHL Vd.2D,Vn.2D,#n

a → Vn.2D

0 << n << 63

Vd.2D → result

v7/A32/A64

Shift left.

SHL Dd,Dn,#n

a → Dn

0 << n << 63

Dd → result

A64

Shift left.

SHL Dd,Dn,#n

a → Dn

0 << n << 63

Dd → result

A64

Signed rounding shift right.

SRSHR Vd.8B,Vn.8B,#n

a → Vn.8B

1 << n << 8

Vd.8B → result

v7/A32/A64

Signed rounding shift right.

SRSHR Vd.16B,Vn.16B,#n

a → Vn.16B

1 << n << 8

Vd.16B → result

v7/A32/A64

Signed rounding shift right.

SRSHR Vd.4H,Vn.4H,#n

a → Vn.4H

1 << n << 16

Vd.4H → result

v7/A32/A64

Signed rounding shift right.

SRSHR Vd.8H,Vn.8H,#n

a → Vn.8H

1 << n << 16

Vd.8H → result

v7/A32/A64

Signed rounding shift right.

SRSHR Vd.2S,Vn.2S,#n

a → Vn.2S

1 << n << 32

Vd.2S → result

v7/A32/A64

Signed rounding shift right.

SRSHR Vd.4S,Vn.4S,#n

a → Vn.4S

1 << n << 32

Vd.4S → result

v7/A32/A64

Signed rounding shift right.

SRSHR Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

v7/A32/A64

Signed rounding shift right.

SRSHR Vd.2D,Vn.2D,#n

a → Vn.2D

1 << n << 64

Vd.2D → result

v7/A32/A64

Unsigned rounding shift right.

URSHR Vd.8B,Vn.8B,#n

a → Vn.8B

1 << n << 8

Vd.8B → result

v7/A32/A64

Unsigned rounding shift right.

URSHR Vd.16B,Vn.16B,#n

a → Vn.16B

1 << n << 8

Vd.16B → result

v7/A32/A64

Unsigned rounding shift right.

URSHR Vd.4H,Vn.4H,#n

a → Vn.4H

1 << n << 16

Vd.4H → result

v7/A32/A64

Unsigned rounding shift right.

URSHR Vd.8H,Vn.8H,#n

a → Vn.8H

1 << n << 16

Vd.8H → result

v7/A32/A64

Unsigned rounding shift right.

URSHR Vd.2S,Vn.2S,#n

a → Vn.2S

1 << n << 32

Vd.2S → result

v7/A32/A64

Unsigned rounding shift right.

URSHR Vd.4S,Vn.4S,#n

a → Vn.4S

1 << n << 32

Vd.4S → result

v7/A32/A64

Unsigned rounding shift right.

URSHR Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

v7/A32/A64

Unsigned rounding shift right.

URSHR Vd.2D,Vn.2D,#n

a → Vn.2D

1 << n << 64

Vd.2D → result

v7/A32/A64

Signed rounding shift right.

SRSHR Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

A64

Unsigned rounding shift right.

URSHR Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

A64

Signed shift right and accumulate.

SSRA Vd.8B,Vn.8B,#n

a → Vd.8B

b → Vn.8B

1 << n << 8

Vd.8B → result

v7/A32/A64

Signed shift right and accumulate.

SSRA Vd.16B,Vn.16B,#n

a → Vd.16B

b → Vn.16B

1 << n << 8

Vd.16B → result

v7/A32/A64

Signed shift right and accumulate.

SSRA Vd.4H,Vn.4H,#n

a → Vd.4H

b → Vn.4H

1 << n << 16

Vd.4H → result

v7/A32/A64

Signed shift right and accumulate.

SSRA Vd.8H,Vn.8H,#n

a → Vd.8H

b → Vn.8H

1 << n << 16

Vd.8H → result

v7/A32/A64

Signed shift right and accumulate.

SSRA Vd.2S,Vn.2S,#n

a → Vd.2S

b → Vn.2S

1 << n << 32

Vd.2S → result

v7/A32/A64

Signed shift right and accumulate.

SSRA Vd.4S,Vn.4S,#n

a → Vd.4S

b → Vn.4S

1 << n << 32

Vd.4S → result

v7/A32/A64

Signed shift right and accumulate.

SSRA Dd,Dn,#n

a → Dd

b → Dn

1 << n << 64

Dd → result

v7/A32/A64

Signed shift right and accumulate.

SSRA Vd.2D,Vn.2D,#n

a → Vd.2D

b → Vn.2D

1 << n << 64

Vd.2D → result

v7/A32/A64

Unsigned shift right and accumulate.

USRA Vd.8B,Vn.8B,#n

a → Vd.8B

b → Vn.8B

1 << n << 8

Vd.8B → result

v7/A32/A64

Unsigned shift right and accumulate.

USRA Vd.16B,Vn.16B,#n

a → Vd.16B

b → Vn.16B

1 << n << 8

Vd.16B → result

v7/A32/A64

Unsigned shift right and accumulate.

USRA Vd.4H,Vn.4H,#n

a → Vd.4H

b → Vn.4H

1 << n << 16

Vd.4H → result

v7/A32/A64

Unsigned shift right and accumulate.

USRA Vd.8H,Vn.8H,#n

a → Vd.8H

b → Vn.8H

1 << n << 16

Vd.8H → result

v7/A32/A64

Unsigned shift right and accumulate.

USRA Vd.2S,Vn.2S,#n

a → Vd.2S

b → Vn.2S

1 << n << 32

Vd.2S → result

v7/A32/A64

Unsigned shift right and accumulate.

USRA Vd.4S,Vn.4S,#n

a → Vd.4S

b → Vn.4S

1 << n << 32

Vd.4S → result

v7/A32/A64

Unsigned shift right and accumulate.

USRA Dd,Dn,#n

a → Dd

b → Dn

1 << n << 64

Dd → result

v7/A32/A64

Unsigned shift right and accumulate.

USRA Vd.2D,Vn.2D,#n

a → Vd.2D

b → Vn.2D

1 << n << 64

Vd.2D → result

v7/A32/A64

Signed shift right and accumulate.

SSRA Dd,Dn,#n

a → Dd

b → Dn

1 << n << 64

Dd → result

A64

Unsigned shift right and accumulate.

USRA Dd,Dn,#n

a → Dd

b → Dn

1 << n << 64

Dd → result

A64

Signed rounding shift right and accumulate.

SRSRA Vd.8B,Vn.8B,#n

a → Vd.8B

b → Vn.8B

1 << n << 8

Vd.8B → result

v7/A32/A64

Signed rounding shift right and accumulate.

SRSRA Vd.16B,Vn.16B,#n

a → Vd.16B

b → Vn.16B

1 << n << 8

Vd.16B → result

v7/A32/A64

Signed rounding shift right and accumulate.

SRSRA Vd.4H,Vn.4H,#n

a → Vd.4H

b → Vn.4H

1 << n << 16

Vd.4H → result

v7/A32/A64

Signed rounding shift right and accumulate.

SRSRA Vd.8H,Vn.8H,#n

a → Vd.8H

b → Vn.8H

1 << n << 16

Vd.8H → result

v7/A32/A64

Signed rounding shift right and accumulate.

SRSRA Vd.2S,Vn.2S,#n

a → Vd.2S

b → Vn.2S

1 << n << 32

Vd.2S → result

v7/A32/A64

Signed rounding shift right and accumulate.

SRSRA Vd.4S,Vn.4S,#n

a → Vd.4S

b → Vn.4S

1 << n << 32

Vd.4S → result

v7/A32/A64

Signed rounding shift right and accumulate.

SRSRA Dd,Dn,#n

a → Dd

b → Dn

1 << n << 64

Dd → result

v7/A32/A64

Signed rounding shift right and accumulate.

SRSRA Vd.2D,Vn.2D,#n

a → Vd.2D

b → Vn.2D

1 << n << 64

Vd.2D → result

v7/A32/A64

Unsigned rounding shift right and accumulate.

URSRA Vd.8B,Vn.8B,#n

a → Vd.8B

b → Vn.8B

1 << n << 8

Vd.8B → result

v7/A32/A64

Unsigned rounding shift right and accumulate.

URSRA Vd.16B,Vn.16B,#n

a → Vd.16B

b → Vn.16B

1 << n << 8

Vd.16B → result

v7/A32/A64

Unsigned rounding shift right and accumulate.

URSRA Vd.4H,Vn.4H,#n

a → Vd.4H

b → Vn.4H

1 << n << 16

Vd.4H → result

v7/A32/A64

Unsigned rounding shift right and accumulate.

URSRA Vd.8H,Vn.8H,#n

a → Vd.8H

b → Vn.8H

1 << n << 16

Vd.8H → result

v7/A32/A64

Unsigned rounding shift right and accumulate.

URSRA Vd.2S,Vn.2S,#n

a → Vd.2S

b → Vn.2S

1 << n << 32

Vd.2S → result

v7/A32/A64

Unsigned rounding shift right and accumulate.

URSRA Vd.4S,Vn.4S,#n

a → Vd.4S

b → Vn.4S

1 << n << 32

Vd.4S → result

v7/A32/A64

Unsigned rounding shift right and accumulate.

URSRA Dd,Dn,#n

a → Dd

b → Dn

1 << n << 64

Dd → result

v7/A32/A64

Unsigned rounding shift right and accumulate.

URSRA Vd.2D,Vn.2D,#n

a → Vd.2D

b → Vn.2D

1 << n << 64

Vd.2D → result

v7/A32/A64

Signed rounding shift right and accumulate.

SRSRA Dd,Dn,#n

a → Dd

b → Dn

1 << n << 64

Dd → result

A64

Unsigned rounding shift right and accumulate.

URSRA Dd,Dn,#n

a → Dd

b → Dn

1 << n << 64

Dd → result

A64

Signed saturating shift left.

SQSHL Vd.8B,Vn.8B,#n

a → Vn.8B

0 << n << 7

Vd.8B → result

v7/A32/A64

Signed saturating shift left.

SQSHL Vd.16B,Vn.16B,#n

a → Vn.16B

0 << n << 7

Vd.16B → result

v7/A32/A64

Signed saturating shift left.

SQSHL Vd.4H,Vn.4H,#n

a → Vn.4H

0 << n << 15

Vd.4H → result

v7/A32/A64

Signed saturating shift left.

SQSHL Vd.8H,Vn.8H,#n

a → Vn.8H

0 << n << 15

Vd.8H → result

v7/A32/A64

Signed saturating shift left.

SQSHL Vd.2S,Vn.2S,#n

a → Vn.2S

0 << n << 31

Vd.2S → result

v7/A32/A64

Signed saturating shift left.

SQSHL Vd.4S,Vn.4S,#n

a → Vn.4S

0 << n << 31

Vd.4S → result

v7/A32/A64

Signed saturating shift left.

SQSHL Dd,Dn,#n

a → Dn

0 << n << 63

Dd → result

v7/A32/A64

Signed saturating shift left.

SQSHL Vd.2D,Vn.2D,#n

a → Vn.2D

0 << n << 63

Vd.2D → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Vd.8B,Vn.8B,#n

a → Vn.8B

0 << n << 7

Vd.8B → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Vd.16B,Vn.16B,#n

a → Vn.16B

0 << n << 7

Vd.16B → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Vd.4H,Vn.4H,#n

a → Vn.4H

0 << n << 15

Vd.4H → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Vd.8H,Vn.8H,#n

a → Vn.8H

0 << n << 15

Vd.8H → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Vd.2S,Vn.2S,#n

a → Vn.2S

0 << n << 31

Vd.2S → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Vd.4S,Vn.4S,#n

a → Vn.4S

0 << n << 31

Vd.4S → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Dd,Dn,#n

a → Dn

0 << n << 63

Dd → result

v7/A32/A64

Unsigned saturating shift left.

UQSHL Vd.2D,Vn.2D,#n

a → Vn.2D

0 << n << 63

Vd.2D → result

v7/A32/A64

Signed saturating shift left.

SQSHL Bd,Bn,#n

a → Bn

0 << n << 7

Bd → result

A64

Signed saturating shift left.

SQSHL Hd,Hn,#n

a → Hn

0 << n << 15

Hd → result

A64

Signed saturating shift left.

SQSHL Sd,Sn,#n

a → Sn

0 << n << 31

Sd → result

A64

Signed saturating shift left.

SQSHL Dd,Dn,#n

a → Dn

0 << n << 63

Dd → result

A64

Unsigned saturating shift left.

UQSHL Bd,Bn,#n

a → Bn

0 << n << 7

Bd → result

A64

Unsigned saturating shift left.

UQSHL Hd,Hn,#n

a → Hn

0 << n << 15

Hd → result

A64

Unsigned saturating shift left.

UQSHL Sd,Sn,#n

a → Sn

0 << n << 31

Sd → result

A64

Unsigned saturating shift left.

UQSHL Dd,Dn,#n

a → Dn

0 << n << 63

Dd → result

A64

Signed saturating shift left unsigned.

SQSHLU Vd.8B,Vn.8B,#n

a → Vn.8B

0 << n << 7

Vd.8B → result

v7/A32/A64

Signed saturating shift left unsigned.

SQSHLU Vd.16B,Vn.16B,#n

a → Vn.16B

0 << n << 7

Vd.16B → result

v7/A32/A64

Signed saturating shift left unsigned.

SQSHLU Vd.4H,Vn.4H,#n

a → Vn.4H

0 << n << 15

Vd.4H → result

v7/A32/A64

Signed saturating shift left unsigned.

SQSHLU Vd.8H,Vn.8H,#n

a → Vn.8H

0 << n << 15

Vd.8H → result

v7/A32/A64

Signed saturating shift left unsigned.

SQSHLU Vd.2S,Vn.2S,#n

a → Vn.2S

0 << n << 31

Vd.2S → result

v7/A32/A64

Signed saturating shift left unsigned.

SQSHLU Vd.4S,Vn.4S,#n

a → Vn.4S

0 << n << 31

Vd.4S → result

v7/A32/A64

Signed saturating shift left unsigned.

SQSHLU Dd,Dn,#n

a → Dn

0 << n << 63

Dd → result

v7/A32/A64

Signed saturating shift left unsigned.

SQSHLU Vd.2D,Vn.2D,#n

a → Vn.2D

0 << n << 63

Vd.2D → result

v7/A32/A64

Signed saturating shift left unsigned.

SQSHLU Bd,Bn,#n

a → Bn

0 << n << 7

Bd → result

A64

Signed saturating shift left unsigned.

SQSHLU Hd,Hn,#n

a → Hn

0 << n << 15

Hd → result

A64

Signed saturating shift left unsigned.

SQSHLU Sd,Sn,#n

a → Sn

0 << n << 31

Sd → result

A64

Signed saturating shift left unsigned.

SQSHLU Dd,Dn,#n

a → Dn

0 << n << 63

Dd → result

A64

Shift right narrow.

SHRN Vd.8B,Vn.8H,#n

a → Vn.8H

1 << n << 8

Vd.8B → result

v7/A32/A64

Shift right narrow.

SHRN Vd.4H,Vn.4S,#n

a → Vn.4S

1 << n << 16

Vd.4H → result

v7/A32/A64

Shift right narrow.

SHRN Vd.2S,Vn.2D,#n

a → Vn.2D

1 << n << 32

Vd.2S → result

v7/A32/A64

Shift right narrow.

SHRN Vd.8B,Vn.8H,#n

a → Vn.8H

1 << n << 8

Vd.8B → result

v7/A32/A64

Shift right narrow.

SHRN Vd.4H,Vn.4S,#n

a → Vn.4S

1 << n << 16

Vd.4H → result

v7/A32/A64

Shift right narrow.

SHRN Vd.2S,Vn.2D,#n

a → Vn.2D

1 << n << 32

Vd.2S → result

v7/A32/A64

Shift right narrow.

SHRN2 Vd.16B,Vn.8H,#n

r → Vd.8B

a → Vn.8H

1 << n << 8

Vd.16B → result

A64

Shift right narrow.

SHRN2 Vd.8H,Vn.4S,#n

r → Vd.4H

a → Vn.4S

1 << n << 16

Vd.8H → result

A64

Shift right narrow.

SHRN2 Vd.4S,Vn.2D,#n

r → Vd.2S

a → Vn.2D

1 << n << 32

Vd.4S → result

A64

Shift right narrow.

SHRN2 Vd.16B,Vn.8H,#n

r → Vd.8B

a → Vn.8H

1 << n << 8

Vd.16B → result

A64

Shift right narrow.

SHRN2 Vd.8H,Vn.4S,#n

r → Vd.4H

a → Vn.4S

1 << n << 16

Vd.8H → result

A64

Shift right narrow.

SHRN2 Vd.4S,Vn.2D,#n

r → Vd.2S

a → Vn.2D

1 << n << 32

Vd.4S → result

A64

Signed saturating shift right unsigned narrow.

SQSHRUN Vd.8B,Vn.8H,#n

a → Vn.8H

1 << n << 8

Vd.8B → result

v7/A32/A64

Signed saturating shift right unsigned narrow.

SQSHRUN Vd.4H,Vn.4S,#n

a → Vn.4S

1 << n << 16

Vd.4H → result

v7/A32/A64

Signed saturating shift right unsigned narrow.

SQSHRUN Vd.2S,Vn.2D,#n

a → Vn.2D

1 << n << 32

Vd.2S → result

v7/A32/A64

Signed saturating shift right unsigned narrow.

SQSHRUN Bd,Hn,#n

a → Hn

1 << n << 8

Bd → result

A64

Signed saturating shift right unsigned narrow.

SQSHRUN Hd,Sn,#n

a → Sn

1 << n << 16

Hd → result

A64

Signed saturating shift right unsigned narrow.

SQSHRUN Sd,Dn,#n

a → Dn

1 << n << 32

Sd → result

A64

Signed saturating shift right unsigned narrow.

SQSHRUN2 Vd.16B,Vn.8H,#n

r → Vd.8B

a → Vn.8H

1 << n << 8

Vd.16B → result

A64

Signed saturating shift right unsigned narrow.

SQSHRUN2 Vd.8H,Vn.4S,#n

r → Vd.4H

a → Vn.4S

1 << n << 16

Vd.8H → result

A64

Signed saturating shift right unsigned narrow.

SQSHRUN2 Vd.4S,Vn.2D,#n

r → Vd.2S

a → Vn.2D

1 << n << 32

Vd.4S → result

A64

Signed saturating rounded shift right unsigned narrow.

SQRSHRUN Vd.8B,Vn.8H,#n

a → Vn.8H

1 << n << 8

Vd.8B → result

v7/A32/A64

Signed saturating rounded shift right unsigned narrow.

SQRSHRUN Vd.4H,Vn.4S,#n

a → Vn.4S

1 << n << 16

Vd.4H → result

v7/A32/A64

Signed saturating rounded shift right unsigned narrow.

SQRSHRUN Vd.2S,Vn.2D,#n

a → Vn.2D

1 << n << 32

Vd.2S → result

v7/A32/A64

Signed saturating rounded shift right unsigned narrow.

SQRSHRUN Bd,Hn,#n

a → Hn

1 << n << 8

Bd → result

A64

Signed saturating rounded shift right unsigned narrow.

SQRSHRUN Hd,Sn,#n

a → Sn

1 << n << 16

Hd → result

A64

Signed saturating rounded shift right unsigned narrow.

SQRSHRUN Sd,Dn,#n

a → Dn

1 << n << 32

Sd → result

A64

Signed saturating rounded shift right unsigned narrow.

SQRSHRUN2 Vd.16B,Vn.8H,#n

r → Vd.8B

a → Vn.8H

1 << n << 8

Vd.16B → result

A64

Signed saturating rounded shift right unsigned narrow.

SQRSHRUN2 Vd.8H,Vn.4S,#n

r → Vd.4H

a → Vn.4S

1 << n << 16

Vd.8H → result

A64

Signed saturating rounded shift right unsigned narrow.

SQRSHRUN2 Vd.4S,Vn.2D,#n

r → Vd.2S

a → Vn.2D

1 << n << 32

Vd.4S → result

A64

Signed saturating shift right narrow.

SQSHRN Vd.8B,Vn.8H,#n

a → Vn.8H

1 << n << 8

Vd.8B → result

v7/A32/A64

Signed saturating shift right narrow.

SQSHRN Vd.4H,Vn.4S,#n

a → Vn.4S

1 << n << 16

Vd.4H → result

v7/A32/A64

Signed saturating shift right narrow.

SQSHRN Vd.2S,Vn.2D,#n

a → Vn.2D

1 << n << 32

Vd.2S → result

v7/A32/A64

Unsigned saturating shift right narrow.

UQSHRN Vd.8B,Vn.8H,#n

a → Vn.8H

1 << n << 8

Vd.8B → result

v7/A32/A64

Unsigned saturating shift right narrow.

UQSHRN Vd.4H,Vn.4S,#n

a → Vn.4S

1 << n << 16

Vd.4H → result

v7/A32/A64

Unsigned saturating shift right narrow.

UQSHRN Vd.2S,Vn.2D,#n

a → Vn.2D

1 << n << 32

Vd.2S → result

v7/A32/A64

Signed saturating shift right narrow.

SQSHRN Bd,Hn,#n

a → Hn

1 << n << 8

Bd → result

A64

Signed saturating shift right narrow.

SQSHRN Hd,Sn,#n

a → Sn

1 << n << 16

Hd → result

A64

Signed saturating shift right narrow.

SQSHRN Sd,Dn,#n

a → Dn

1 << n << 32

Sd → result

A64

Unsigned saturating shift right narrow.

UQSHRN Bd,Hn,#n

a → Hn

1 << n << 8

Bd → result

A64

Unsigned saturating shift right narrow.

UQSHRN Hd,Sn,#n

a → Sn

1 << n << 16

Hd → result

A64

Unsigned saturating shift right narrow.

UQSHRN Sd,Dn,#n

a → Dn

1 << n << 32

Sd → result

A64

Signed saturating shift right narrow.

SQSHRN2 Vd.16B,Vn.8H,#n

r → Vd.8B

a → Vn.8H

1 << n << 8

Vd.16B → result

A64

Signed saturating shift right narrow.

SQSHRN2 Vd.8H,Vn.4S,#n

r → Vd.4H

a → Vn.4S

1 << n << 16

Vd.8H → result

A64

Signed saturating shift right narrow.

SQSHRN2 Vd.4S,Vn.2D,#n

r → Vd.2S

a → Vn.2D

1 << n << 32

Vd.4S → result

A64

Unsigned saturating shift right narrow.

UQSHRN2 Vd.16B,Vn.8H,#n

r → Vd.8B

a → Vn.8H

1 << n << 8

Vd.16B → result

A64

Unsigned saturating shift right narrow.

UQSHRN2 Vd.8H,Vn.4S,#n

r → Vd.4H

a → Vn.4S

1 << n << 16

Vd.8H → result

A64

Unsigned saturating shift right narrow.

UQSHRN2 Vd.4S,Vn.2D,#n

r → Vd.2S

a → Vn.2D

1 << n << 32

Vd.4S → result

A64

Rounding shift right narrow.

RSHRN Vd.8B,Vn.8H,#n

a → Vn.8H

1 << n << 8

Vd.8B → result

v7/A32/A64

Rounding shift right narrow.

RSHRN Vd.4H,Vn.4S,#n

a → Vn.4S

1 << n << 16

Vd.4H → result

v7/A32/A64

Rounding shift right narrow.

RSHRN Vd.2S,Vn.2D,#n

a → Vn.2D

1 << n << 32

Vd.2S → result

v7/A32/A64

Rounding shift right narrow.

RSHRN Vd.8B,Vn.8H,#n

a → Vn.8H

1 << n << 8

Vd.8B → result

v7/A32/A64

Rounding shift right narrow.

RSHRN Vd.4H,Vn.4S,#n

a → Vn.4S

1 << n << 16

Vd.4H → result

v7/A32/A64

Rounding shift right narrow.

RSHRN Vd.2S,Vn.2D,#n

a → Vn.2D

1 << n << 32

Vd.2S → result

v7/A32/A64

Rounding shift right narrow.

RSHRN2 Vd.16B,Vn.8H,#n

r → Vd.8B

a → Vn.8H

1 << n << 8

Vd.16B → result

A64

Rounding shift right narrow.

RSHRN2 Vd.8H,Vn.4S,#n

r → Vd.4H

a → Vn.4S

1 << n << 16

Vd.8H → result

A64

Rounding shift right narrow.

RSHRN2 Vd.4S,Vn.2D,#n

r → Vd.2S

a → Vn.2D

1 << n << 32

Vd.4S → result

A64

Rounding shift right narrow.

RSHRN2 Vd.16B,Vn.8H,#n

r → Vd.8B

a → Vn.8H

1 << n << 8

Vd.16B → result

A64

Rounding shift right narrow.

RSHRN2 Vd.8H,Vn.4S,#n

r → Vd.4H

a → Vn.4S

1 << n << 16

Vd.8H → result

A64

Rounding shift right narrow.

RSHRN2 Vd.4S,Vn.2D,#n

r → 32(Vd)

a → Vn.2D

1 << n << 32

Vd.4S → result

A64

Signed saturating rounded shift right narrow.

SQRSHRN Vd.8B,Vn.8H,#n

a → Vn.8H

1 << n << 8

Vd.8B → result

v7/A32/A64

Signed saturating rounded shift right narrow.

SQRSHRN Vd.4H,Vn.4S,#n

a → Vn.4S

1 << n << 16

Vd.4H → result

v7/A32/A64

Signed saturating rounded shift right narrow.

SQRSHRN Vd.2S,Vn.2D,#n

a → Vn.2D

1 << n << 32

Vd.2S → result

v7/A32/A64

Unsigned saturating rounded shift right narrow.

UQRSHRN Vd.8B,Vn.8H,#n

a → Vn.8H

1 << n << 8

Vd.8B → result

v7/A32/A64

Unsigned saturating rounded shift right narrow.

UQRSHRN Vd.4H,Vn.4S,#n

a → Vn.4S

1 << n << 16

Vd.4H → result

v7/A32/A64

Unsigned saturating rounded shift right narrow.

UQRSHRN Vd.2S,Vn.2D,#n

a → Vn.2D

1 << n << 32

Vd.2S → result

v7/A32/A64

Signed saturating rounded shift right narrow.

SQRSHRN Bd,Hn,#n

a → Hn

1 << n << 8

Bd → result

A64

Signed saturating rounded shift right narrow.

SQRSHRN Hd,Sn,#n

a → Sn

1 << n << 16

Hd → result

A64

Signed saturating rounded shift right narrow.

SQRSHRN Sd,Dn,#n

a → Dn

1 << n << 32

Sd → result

A64

Unsigned saturating rounded shift right narrow.

UQRSHRN Bd,Hn,#n

a → Hn

1 << n << 8

Bd → result

A64

Unsigned saturating rounded shift right narrow.

UQRSHRN Hd,Sn,#n

a → Sn

1 << n << 16

Hd → result

A64

Unsigned saturating rounded shift right narrow.

UQRSHRN Sd,Dn,#n

a → Dn

1 << n << 32

Sd → result

A64

Signed saturating rounded shift right narrow.

SQRSHRN2 Vd.16B,Vn.8H,#n

r → Vd.8B

a → Vn.8H

1 << n << 8

Vd.16B → result

A64

Signed saturating rounded shift right narrow.

SQRSHRN2 Vd.8H,Vn.4S,#n

r → Vd.4H

a → Vn.4S

1 << n << 16

Vd.8H → result

A64

Signed saturating rounded shift right narrow.

SQRSHRN2 Vd.4S,Vn.2D,#n

r → Vd.2S

a → Vn.2D

1 << n << 32

Vd.4S → result

A64

Unsigned saturating rounded shift right narrow.

UQRSHRN2 Vd.16B,Vn.8H,#n

r → Vd.8B

a → Vn.8H

1 << n << 8

Vd.16B → result

A64

Unsigned saturating rounded shift right narrow.

UQRSHRN2 Vd.8H,Vn.4S,#n

r → Vd.4H

a → Vn.4S

1 << n << 16

Vd.8H → result

A64

Unsigned saturating rounded shift right narrow.

UQRSHRN2 Vd.4S,Vn.2D,#n

r → Vd.2S

a → Vn.2D

1 << n << 32

Vd.4S → result

A64

Signed shift left long.

SSHLL Vd.8H,Vn.8B,#n

a → Vn.8B

0 << n << 7

Vd.8H → result

v7/A32/A64

Signed shift left long.

SSHLL Vd.4S,Vn.4H,#n

a → Vn.4H

0 << n << 15

Vd.4S → result

v7/A32/A64

Signed shift left long.

SSHLL Vd.2D,Vn.2S,#n

a → Vn.2S

0 << n << 31

Vd.2D → result

v7/A32/A64

Unsigned shift left long.

USHLL Vd.8H,Vn.8B,#n

a → Vn.8B

0 << n << 7

Vd.8H → result

v7/A32/A64

Unsigned shift left long.

USHLL Vd.4S,Vn.4H,#n

a → Vn.4H

0 << n << 15

Vd.4S → result

v7/A32/A64

Unsigned shift left long.

USHLL Vd.2D,Vn.2S,#n

a → Vn.2S

0 << n << 31

Vd.2D → result

v7/A32/A64

Signed shift left long.

SSHLL2 Vd.8H,Vn.16B,#n

a → Vn.16B

0 << n << 7

Vd.8H → result

A64

Signed shift left long.

SSHLL2 Vd.4S,Vn.8H,#n

a → Vn.8H

0 << n << 15

Vd.4S → result

A64

Signed shift left long.

SSHLL2 Vd.2D,Vn.4S,#n

a → Vn.4S

0 << n << 31

Vd.2D → result

A64

Unsigned shift left long.

USHLL2 Vd.8H,Vn.16B,#n

a → Vn.16B

0 << n << 7

Vd.8H → result

A64

Unsigned shift left long.

USHLL2 Vd.4S,Vn.8H,#n

a → Vn.8H

0 << n << 15

Vd.4S → result

A64

Unsigned shift left long.

USHLL2 Vd.2D,Vn.4S,#n

a → Vn.4S

0 << n << 31

Vd.2D → result

A64

Shift left long.

SHLL Vd.8H,Vn.8B,#n

a → Vn.8B

8 << n << 8

Vd.8H → result

v7/A32/A64

Shift left long.

SHLL Vd.4S,Vn.4H,#n

a → Vn.4H

16 << n << 16

Vd.4S → result

v7/A32/A64

Shift left long.

SHLL Vd.2D,Vn.2S,#n

a → Vn.2S

32 << n << 32

Vd.2D → result

v7/A32/A64

Shift left long.

SHLL Vd.8H,Vn.8B,#n

a → Vn.8B

8 << n << 8

Vd.8H → result

v7/A32/A64

Shift left long.

SHLL Vd.4S,Vn.4H,#n

a → Vn.4H

16 << n << 16

Vd.4S → result

v7/A32/A64

Shift left long.

SHLL Vd.2D,Vn.2S,#n

a → Vn.2S

32 << n << 32

Vd.2D → result

v7/A32/A64

Shift left long.

SHLL2 Vd.8H,Vn.16B,#n

a → Vn.16B

8 << n << 8

Vd.8H → result

A64

Shift left long.

SHLL2 Vd.4S,Vn.8H,#n

a → Vn.8H

16 << n << 16

Vd.4S → result

A64

Shift left long.

SHLL2 Vd.2D,Vn.4S,#n

a → Vn.4S

32 << n << 32

Vd.2D → result

A64

Shift left long.

SHLL2 Vd.8H,Vn.16B,#n

a → Vn.16B

8 << n << 8

Vd.8H → result

A64

Shift left long.

SHLL2 Vd.4S,Vn.8H,#n

a → Vn.8H

16 << n << 16

Vd.4S → result

A64

Shift left long.

SHLL2 Vd.2D,Vn.4S,#n

a → Vn.4S

32 << n << 32

Vd.2D → result

A64

Shift right and insert.

SRI Vd.8B,Vn.8B,#n

a → Vd.8B

b → Vn.8B

1 << n << 8

Vd.8B → result

v7/A32/A64

Shift right and insert.

SRI Vd.16B,Vn.16B,#n

a → Vd.16B

b → Vn.16B

1 << n << 8

Vd.16B → result

v7/A32/A64

Shift right and insert.

SRI Vd.4H,Vn.4H,#n

a → Vd.4H

b → Vn.4H

1 << n << 16

Vd.4H → result

v7/A32/A64

Shift right and insert.

SRI Vd.8H,Vn.8H,#n

a → Vd.8H

b → Vn.8H

1 << n << 16

Vd.8H → result

v7/A32/A64

Shift right and insert.

SRI Vd.2S,Vn.2S,#n

a → Vd.2S

b → Vn.2S

1 << n << 32

Vd.2S → result

v7/A32/A64

Shift right and insert.

SRI Vd.4S,Vn.4S,#n

a → Vd.4S

b → Vn.4S

1 << n << 32

Vd.4S → result

v7/A32/A64

Shift right and insert.

SRI Dd,Dn,#n

a → Dd

b → Dn

1 << n << 64

Dd → result

v7/A32/A64

Shift right and insert.

SRI Vd.2D,Vn.2D,#n

a → Vd.2D

b → Vn.2D

1 << n << 64

Vd.2D → result

v7/A32/A64

Shift right and insert.

SRI Vd.8B,Vn.8B,#n

a → Vd.8B

b → Vn.8B

1 << n << 8

Vd.8B → result

v7/A32/A64

Shift right and insert.

SRI Vd.16B,Vn.16B,#n

a → Vd.16B

b → Vn.16B

1 << n << 8

Vd.16B → result

v7/A32/A64

Shift right and insert.

SRI Vd.4H,Vn.4H,#n

a → Vd.4H

b → Vn.4H

1 << n << 16

Vd.4H → result

v7/A32/A64

Shift right and insert.

SRI Vd.8H,Vn.8H,#n

a → Vd.8H

b → Vn.8H

1 << n << 16

Vd.8H → result

v7/A32/A64

Shift right and insert.

SRI Vd.2S,Vn.2S,#n

a → Vd.2S

b → Vn.2S

1 << n << 32

Vd.2S → result

v7/A32/A64

Shift right and insert.

SRI Vd.4S,Vn.4S,#n

a → Vd.4S

b → Vn.4S

1 << n << 32

Vd.4S → result

v7/A32/A64

Shift right and insert.

SRI Dd,Dn,#n

a → Dd

b → Dn

1 << n << 64

Dd → result

v7/A32/A64

Shift right and insert.

SRI Vd.2D,Vn.2D,#n

a → Vd.2D

b → Vn.2D

1 << n << 64

Vd.2D → result

v7/A32/A64

Shift right and insert.

SRI Dd,Dn,#n

a → Dd

b → Dn

1 << n << 64

Dd → result

A32/A64

Shift right and insert.

SRI Vd.2D,Vn.2D,#n

a → Vd.2D

b → Vn.2D

1 << n << 64

Vd.2D → result

A32/A64

Shift right and insert.

SRI Vd.8B,Vn.8B,#n

a → Vd.8B

b → Vn.8B

1 << n << 8

Vd.8B → result

v7/A32/A64

Shift right and insert.

SRI Vd.16B,Vn.16B,#n

a → Vd.16B

b → Vn.16B

1 << n << 8

Vd.16B → result

v7/A32/A64

Shift right and insert.

SRI Vd.4H,Vn.4H,#n

a → Vd.4H

b → Vn.4H

1 << n << 16

Vd.4H → result

v7/A32/A64

Shift right and insert.

SRI Vd.8H,Vn.8H,#n

a → Vd.8H

b → Vn.8H

1 << n << 16

Vd.8H → result

v7/A32/A64

Shift right and insert.

SRI Dd,Dn,#n

a → Dd

b → Dn

1 << n << 64

Dd → result

A64

Shift right and insert.

SRI Dd,Dn,#n

a → Dd

b → Dn

1 << n << 64

Dd → result

A64

Shift left and insert.

SLI Vd.8B,Vn.8B,#n

a → Vd.8B

b → Vn.8B

0 << n << 7

Vd.8B → result

v7/A32/A64

Shift left and insert.

SLI Vd.16B,Vn.16B,#n

a → Vd.16B

b → Vn.16B

0 << n << 7

Vd.16B → result

v7/A32/A64

Shift left and insert.

SLI Vd.4H,Vn.4H,#n

a → Vd.4H

b → Vn.4H

0 << n << 15

Vd.4H → result

v7/A32/A64

Shift left and insert.

SLI Vd.8H,Vn.8H,#n

a → Vd.8H

b → Vn.8H

0 << n << 15

Vd.8H → result

v7/A32/A64

Shift left and insert.

SLI Vd.2S,Vn.2S,#n

a → Vd.2S

b → Vn.2S

0 << n << 31

Vd.2S → result

v7/A32/A64

Shift left and insert.

SLI Vd.4S,Vn.4S,#n

a → Vd.4S

b → Vn.4S

0 << n << 31

Vd.4S → result

v7/A32/A64

Shift left and insert.

SLI Dd,Dn,#n

a → Dd

b → Dn

0 << n << 63

Dd → result

v7/A32/A64

Shift left and insert.

SLI Vd.2D,Vn.2D,#n

a → Vd.2D

b → Vn.2D

0 << n << 63

Vd.2D → result

v7/A32/A64

Shift left and insert.

SLI Vd.8B,Vn.8B,#n

a → Vd.8B

b → Vn.8B

0 << n << 7

Vd.8B → result

v7/A32/A64

Shift left and insert.

SLI Vd.16B,Vn.16B,#n

a → Vd.16B

b → Vn.16B

0 << n << 7

Vd.16B → result

v7/A32/A64

Shift left and insert.

SLI Vd.4H,Vn.4H,#n

a → Vd.4H

b → Vn.4H

0 << n << 15

Vd.4H → result

v7/A32/A64

Shift left and insert.

SLI Vd.8H,Vn.8H,#n

a → Vd.8H

b → Vn.8H

0 << n << 15

Vd.8H → result

v7/A32/A64

Shift left and insert.

SLI Vd.2S,Vn.2S,#n

a → Vd.2S

b → Vn.2S

0 << n << 31

Vd.2S → result

v7/A32/A64

Shift left and insert.

SLI Vd.4S,Vn.4S,#n

a → Vd.4S

b → Vn.4S

0 << n << 31

Vd.4S → result

v7/A32/A64

Shift left and insert.

SLI Dd,Dn,#n

a → Dd

b → Dn

0 << n << 63

Dd → result

v7/A32/A64

Shift left and insert.

SLI Vd.2D,Vn.2D,#n

a → Vd.2D

b → Vn.2D

0 << n << 63

Vd.2D → result

v7/A32/A64

Shift left and insert.

SLI Dd,Dn,#n

a → Dd

b → Dn

0 << n << 63

Dd → result

A32/A64

Shift left and insert.

SLI Vd.2D,Vn.2D,#n

a → Vd.2D

b → Vn.2D

0 << n << 63

Vd.2D → result

A32/A64

Shift left and insert.

SLI Vd.8B,Vn.8B,#n

a → Vd.8B

b → Vn.8B

0 << n << 7

Vd.8B → result

v7/A32/A64

Shift left and insert.

SLI Vd.16B,Vn.16B,#n

a → Vd.16B

b → Vn.16B

0 << n << 7

Vd.16B → result

v7/A32/A64

Shift left and insert.

SLI Vd.4H,Vn.4H,#n

a → Vd.4H

b → Vn.4H

0 << n << 15

Vd.4H → result

v7/A32/A64

Shift left and insert.

SLI Vd.8H,Vn.8H,#n

a → Vd.8H

b → Vn.8H

0 << n << 15

Vd.8H → result

v7/A32/A64

Shift left and insert.

SLI Dd,Dn,#n

a → Dd

b → Dn

0 << n << 63

Dd → result

A64

Shift left and insert.

SLI Dd,Dn,#n

a → Dd

b → Dn

0 << n << 63

Dd → result

A64

Floating-point convert to signed integer, rounding toward zero.

FCVTZS Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

v7/A32/A64

Floating-point convert to signed integer, rounding toward zero.

FCVTZS Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

v7/A32/A64

Floating-point convert to unsigned integer, rounding toward zero.

FCVTZU Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

v7/A32/A64

Floating-point convert to unsigned integer, rounding toward zero.

FCVTZU Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

v7/A32/A64

Floating-point convert to signed integer, rounding to nearest with ties to even.

FCVTNS Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point convert to signed integer, rounding to nearest with ties to even.

FCVTNS Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point convert to unsigned integer, rounding to nearest with ties to even.

FCVTNU Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point convert to unsigned integer, rounding to nearest with ties to even.

FCVTNU Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point convert to signed integer, rounding toward minus infinity.

FCVTMS Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point convert to signed integer, rounding toward minus infinity.

FCVTMS Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point convert to unsigned integer, rounding toward minus infinity.

FCVTMU Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point convert to unsigned integer, rounding toward minus infinity.

FCVTMU Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point convert to signed integer, rounding toward plus infinity.

FCVTPS Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point convert to signed integer, rounding toward plus infinity.

FCVTPS Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point convert to unsigned integer, rounding toward plus infinity.

FCVTPU Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point convert to unsigned integer, rounding toward plus infinity.

FCVTPU Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point convert to signed integer, rounding to nearest with ties to away.

FCVTAS Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point convert to signed integer, rounding to nearest with ties to away.

FCVTAS Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point convert to unsigned integer, rounding to nearest with ties to away.

FCVTAU Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point convert to unsigned integer, rounding to nearest with ties to away.

FCVTAU Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point convert to signed integer, rounding toward zero.

FCVTZS Sd,Sn

a → Sn

Sd → result

A64

Floating-point convert to unsigned integer, rounding toward zero.

FCVTZU Sd,Sn

a → Sn

Sd → result

A64

Floating-point convert to signed integer, rounding to nearest with ties to even.

FCVTNS Sd,Sn

a → Sn

Sd → result

A64

Floating-point convert to unsigned integer, rounding to nearest with ties to even.

FCVTNU Sd,Sn

a → Sn

Sd → result

A64

Floating-point convert to signed integer, rounding toward minus infinity.

FCVTMS Sd,Sn

a → Sn

Sd → result

A64

Floating-point convert to unsigned integer, rounding toward minus infinity.

FCVTMU Sd,Sn

a → Sn

Sd → result

A64

Floating-point convert to signed integer, rounding toward plus infinity.

FCVTPS Sd,Sn

a → Sn

Sd → result

A64

Floating-point convert to unsigned integer, rounding toward plus infinity.

FCVTPU Sd,Sn

a → Sn

Sd → result

A64

Floating-point convert to signed integer, rounding to nearest with ties to away.

FCVTAS Sd,Sn

a → Sn

Sd → result

A64

Floating-point convert to unsigned integer, rounding to nearest with ties to away.

FCVTAU Sd,Sn

a → Sn

Sd → result

A64

Floating-point convert to signed integer, rounding toward zero.

FCVTZS Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to signed integer, rounding toward zero.

FCVTZS Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point convert to unsigned integer, rounding toward zero.

FCVTZU Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to unsigned integer, rounding toward zero.

FCVTZU Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point convert to signed integer, rounding to nearest with ties to even.

FCVTNS Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to signed integer, rounding to nearest with ties to even.

FCVTNS Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point convert to unsigned integer, rounding to nearest with ties to even.

FCVTNU Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to unsigned integer, rounding to nearest with ties to even.

FCVTNU Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point convert to signed integer, rounding toward minus infinity.

FCVTMS Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to signed integer, rounding toward minus infinity.

FCVTMS Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point convert to unsigned integer, rounding toward minus infinity.

FCVTMU Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to unsigned integer, rounding toward minus infinity.

FCVTMU Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point convert to signed integer, rounding toward plus infinity.

FCVTPS Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to signed integer, rounding toward plus infinity.

FCVTPS Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point convert to unsigned integer, rounding toward plus infinity.

FCVTPU Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to unsigned integer, rounding toward plus infinity.

FCVTPU Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point convert to signed integer, rounding to nearest with ties to away.

FCVTAS Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to signed integer, rounding to nearest with ties to away.

FCVTAS Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point convert to unsigned integer, rounding to nearest with ties to away.

FCVTAU Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to unsigned integer, rounding to nearest with ties to away.

FCVTAU Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point convert to signed integer, rounding toward zero.

FCVTZS Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to unsigned integer, rounding toward zero.

FCVTZU Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to signed integer, rounding to nearest with ties to even.

FCVTNS Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to unsigned integer, rounding to nearest with ties to even.

FCVTNU Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to signed integer, rounding toward minus infinity.

FCVTMS Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to unsigned integer, rounding toward minus infinity.

FCVTMU Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to signed integer, rounding toward plus infinity.

FCVTPS Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to unsigned integer, rounding toward plus infinity.

FCVTPU Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to signed integer, rounding to nearest with ties to away.

FCVTAS Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to unsigned integer, rounding to nearest with ties to away.

FCVTAU Dd,Dn

a → Dn

Dd → result

A64

Floating-point convert to signed integer, rounding toward zero.

FCVTZS Vd.2S,Vn.2S,#n

a → Vn.2S

1 << n << 32

Vd.2S → result

v7/A32/A64

Floating-point convert to signed integer, rounding toward zero.

FCVTZS Vd.4S,Vn.4S,#n

a → Vn.4S

1 << n << 32

Vd.4S → result

v7/A32/A64

Floating-point convert to unsigned integer, rounding toward zero.

FCVTZU Vd.2S,Vn.2S,#n

a → Vn.2S

1 << n << 32

Vd.2S → result

v7/A32/A64

Floating-point convert to unsigned integer, rounding toward zero.

FCVTZU Vd.4S,Vn.4S,#n

a → Vn.4S

1 << n << 32

Vd.4S → result

v7/A32/A64

Floating-point convert to signed integer, rounding toward zero.

FCVTZS Sd,Sn,#n

a → Sn

1 << n << 32

Sd → result

A64

Floating-point convert to unsigned integer, rounding toward zero.

FCVTZU Sd,Sn,#n

a → Sn

1 << n << 32

Sd → result

A64

Floating-point convert to signed integer, rounding toward zero.

FCVTZS Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

A64

Floating-point convert to signed integer, rounding toward zero.

FCVTZS Vd.2D,Vn.2D,#n

a → Vn.2D

1 << n << 64

Vd.2D → result

A64

Floating-point convert to unsigned integer, rounding toward zero.

FCVTZU Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

A64

Floating-point convert to unsigned integer, rounding toward zero.

FCVTZU Vd.2D,Vn.2D,#n

a → Vn.2D

1 << n << 64

Vd.2D → result

A64

Floating-point convert to signed integer, rounding toward zero.

FCVTZS Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

A64

Floating-point convert to unsigned integer, rounding toward zero.

FCVTZU Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

A64

Signed integer convert to floating-point.

SCVTF Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

v7/A32/A64

Signed integer convert to floating-point.

SCVTF Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

v7/A32/A64

Unsigned integer convert to floating-point.

UCVTF Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

v7/A32/A64

Unsigned integer convert to floating-point.

UCVTF Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

v7/A32/A64

Signed integer convert to floating-point.

SCVTF Sd,Sn

a → Sn

Sd → result

A64

Unsigned integer convert to floating-point.

UCVTF Sd,Sn

a → Sn

Sd → result

A64

Signed integer convert to floating-point.

SCVTF Dd,Dn

a → Dn

Dd → result

A64

Signed integer convert to floating-point.

SCVTF Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Unsigned integer convert to floating-point.

UCVTF Dd,Dn

a → Dn

Dd → result

A64

Unsigned integer convert to floating-point.

UCVTF Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Signed integer convert to floating-point.

SCVTF Dd,Dn

a → Dn

Dd → result

A64

Unsigned integer convert to floating-point.

UCVTF Dd,Dn

a → Dn

Dd → result

A64

Signed integer convert to floating-point.

SCVTF Vd.2S,Vn.2S,#n

a → Vn.2S

1 << n << 32

Vd.2S → result

v7/A32/A64

Signed integer convert to floating-point.

SCVTF Vd.4S,Vn.4S,#n

a → Vn.4S

1 << n << 32

Vd.4S → result

v7/A32/A64

Unsigned integer convert to floating-point.

UCVTF Vd.2S,Vn.2S,#n

a → Vn.2S

1 << n << 32

Vd.2S → result

v7/A32/A64

Unsigned integer convert to floating-point.

UCVTF Vd.4S,Vn.4S,#n

a → Vn.4S

1 << n << 32

Vd.4S → result

v7/A32/A64

Signed integer convert to floating-point.

SCVTF Sd,Sn,#n

a → Sn

1 << n << 32

Sd → result

A64

Unsigned integer convert to floating-point.

UCVTF Sd,Sn,#n

a → Sn

1 << n << 32

Sd → result

A64

Signed integer convert to floating-point.

SCVTF Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

A64

Signed integer convert to floating-point.

SCVTF Vd.2D,Vn.2D,#n

a → Vn.2D

1 << n << 64

Vd.2D → result

A64

Unsigned integer convert to floating-point.

UCVTF Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

A64

Unsigned integer convert to floating-point.

UCVTF Vd.2D,Vn.2D,#n

a → Vn.2D

1 << n << 64

Vd.2D → result

A64

Signed integer convert to floating-point.

SCVTF Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

A64

Unsigned integer convert to floating-point.

UCVTF Dd,Dn,#n

a → Dn

1 << n << 64

Dd → result

A64

Floating-point convert to lower precision narrow.

FCVTN Vd.4H,Vn.4S

a → Vn.4S

Vd.4H → result

v7/A32/A64

Floating-point convert to lower precision narrow.

FCVTN2 Vd.8H,Vn.4S

r → Vd.4H

a → Vn.4S

Vd.8H → result

A64

Floating-point convert to lower precision narrow.

FCVTN Vd.2S,Vn.2D

a → Vn.2D

Vd.2S → result

A64

Floating-point convert to lower precision narrow.

FCVTN2 Vd.4S,Vn.2D

r → Vd.2S

a → Vn.2D

Vd.4S → result

A64

Floating-point convert to higher precision long.

FCVTL Vd.4S,Vn.4H

a → Vn.4H

Vd.4S → result

v7/A32/A64

Floating-point convert to higher precision long.

FCVTL2 Vd.4S,Vn.8H

a → Vn.8H

Vd.4S → result

A64

Floating-point convert to higher precision long.

FCVTL Vd.2D,Vn.2S

a → Vn.2S

Vd.2D → result

A64

Floating-point convert to higher precision long.

FCVTL2 Vd.2D,Vn.4S

a → Vn.4S

Vd.2D → result

A64

Floating-point convert to lower precision narrow, rounding to odd.

FCVTXN Vd.2S,Vn.2D

a → Vn.2D

Vd.2S → result

A64

Floating-point convert to lower precision narrow, rounding to odd.

FCVTXN Sd,Dn

a → Dn

Sd → result

A64

Floating-point convert to lower precision narrow, rounding to odd.

FCVTXN2 Vd.4S,Vn.2D

r → Vd.2S

a → Vn.2D

Vd.4S → result

A64

Floating-point round to integral, toward zero.

FRINTZ Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point round to integral, toward zero.

FRINTZ Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point round to integral, toward zero.

FRINTZ Dd,Dn

a → Dn

Dd → result

A64

Floating-point round to integral, toward zero.

FRINTZ Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point round to integral, to nearest with ties to even.

FRINTN Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point round to integral, to nearest with ties to even.

FRINTN Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point round to integral, to nearest with ties to even.

FRINTN Dd,Dn

a → Dn

Dd → result

A32/A64

Floating-point round to integral, to nearest with ties to even.

FRINTN Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A32/A64

Floating-point round to integral, to nearest with ties to even.

FRINTN Sd,Sn

a → Sn

Sd → result

A32/A64

Floating-point round to integral, toward minus infinity.

FRINTM Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point round to integral, toward minus infinity.

FRINTM Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point round to integral, toward minus infinity.

FRINTM Dd,Dn

a → Dn

Dd → result

A64

Floating-point round to integral, toward minus infinity.

FRINTM Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point round to integral, toward plus infinity.

FRINTP Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point round to integral, toward plus infinity.

FRINTP Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point round to integral, toward plus infinity.

FRINTP Dd,Dn

a → Dn

Dd → result

A64

Floating-point round to integral, toward plus infinity.

FRINTP Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point round to integral, to nearest with ties to away.

FRINTA Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point round to integral, to nearest with ties to away.

FRINTA Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point round to integral, to nearest with ties to away.

FRINTA Dd,Dn

a → Dn

Dd → result

A64

Floating-point round to integral, to nearest with ties to away.

FRINTA Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point round to integral, using current rounding mode.

FRINTI Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point round to integral, using current rounding mode.

FRINTI Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point round to integral, using current rounding mode.

FRINTI Dd,Dn

a → Dn

Dd → result

A64

Floating-point round to integral, using current rounding mode.

FRINTI Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Floating-point round to integral exact, using current rounding mode.

FRINTX Vd.2S,Vn.2S

a → Vn.2S

Vd.2S → result

A32/A64

Floating-point round to integral exact, using current rounding mode.

FRINTX Vd.4S,Vn.4S

a → Vn.4S

Vd.4S → result

A32/A64

Floating-point round to integral exact, using current rounding mode.

FRINTX Dd,Dn

a → Dn

Dd → result

A64

Floating-point round to integral exact, using current rounding mode.

FRINTX Vd.2D,Vn.2D

a → Vn.2D

Vd.2D → result

A64

Extract narrow.

XTN Vd.8B,Vn.8H

a → Vn.8H

Vd.8B → result

v7/A32/A64

Extract narrow.

XTN Vd.4H,Vn.4S

a → Vn.4S

Vd.4H → result

v7/A32/A64

Extract narrow.

XTN Vd.2S,Vn.2D

a → Vn.2D

Vd.2S → result

v7/A32/A64

Extract narrow.

XTN Vd.8B,Vn.8H

a → Vn.8H

Vd.8B → result

v7/A32/A64

Extract narrow.

XTN Vd.4H,Vn.4S

a → Vn.4S

Vd.4H → result

v7/A32/A64

Extract narrow.

XTN Vd.2S,Vn.2D

a → Vn.2D

Vd.2S → result

v7/A32/A64

Extract narrow.

XTN2 Vd.16B,Vn.8H

r → Vd.8B

a → Vn.8H

Vd.16B → result

A64

Extract narrow.

XTN2 Vd.8H,Vn.4S

r → Vd.4H

a → Vn.4S

Vd.8H → result

A64

Extract narrow.

XTN2 Vd.4S,Vn.2D

r → Vd.2S

a → Vn.2D

Vd.4S → result

A64

Extract narrow.

XTN2 Vd.16B,Vn.8H

r → Vd.8B

a → Vn.8H

Vd.16B → result

A64

Extract narrow.

XTN2 Vd.8H,Vn.4S

r → Vd.4H

a → Vn.4S

Vd.8H → result

A64

Extract narrow.

XTN2 Vd.4S,Vn.2D

r → Vd.2S

a → Vn.2D

Vd.4S → result

A64

Signed shift left long.

SSHLL Vd.8H,Vn.8B,#0

a → Vn.8B

Vd.8H → result

v7/A32/A64

Signed shift left long.

SSHLL Vd.4S,Vn.4H,#0

a → Vn.4H

Vd.4S → result

v7/A32/A64

Signed shift left long.

SSHLL Vd.2D,Vn.2S,#0

a → Vn.2S

Vd.2D → result

v7/A32/A64

Unsigned shift left long.

USHLL Vd.8H,Vn.8B,#0

a → Vn.8B

Vd.8H → result

v7/A32/A64

Unsigned shift left long.

USHLL Vd.4S,Vn.4H,#0

a → Vn.4H

Vd.4S → result

v7/A32/A64

Unsigned shift left long.

USHLL Vd.2D,Vn.2S,#0

a → Vn.2S

Vd.2D → result

v7/A32/A64

Signed shift left long.

SSHLL2 Vd.8H,Vn.16B,#0

a → Vn.16B

Vd.8H → result

A64

Signed shift left long.

SSHLL2 Vd.4S,Vn.8H,#0

a → Vn.8H

Vd.4S → result

A64

Signed shift left long.

SSHLL2 Vd.2D,Vn.4S,#0

a → Vn.4S

Vd.2D → result

A64

Unsigned shift left long.

USHLL2 Vd.8H,Vn.16B,#0

a → Vn.16B

Vd.8H → result

A64

Unsigned shift left long.

USHLL2 Vd.4S,Vn.8H,#0

a → Vn.8H

Vd.4S → result

A64

Unsigned shift left long.

USHLL2 Vd.2D,Vn.4S,#0

a → Vn.4S

Vd.2D → result

A64

Signed saturating extract narrow.

SQXTN Vd.8B,Vn.8H

a → Vn.8H

Vd.8B → result

v7/A32/A64

Signed saturating extract narrow.

SQXTN Vd.4H,Vn.4S

a → Vn.4S

Vd.4H → result

v7/A32/A64

Signed saturating extract narrow.

SQXTN Vd.2S,Vn.2D

a → Vn.2D

Vd.2S → result

v7/A32/A64

Unsigned saturating extract narrow.

UQXTN Vd.8B,Vn.8H

a → Vn.8H

Vd.8B → result

v7/A32/A64

Unsigned saturating extract narrow.

UQXTN Vd.4H,Vn.4S

a → Vn.4S

Vd.4H → result

v7/A32/A64

Unsigned saturating extract narrow.

UQXTN Vd.2S,Vn.2D

a → Vn.2D

Vd.2S → result

v7/A32/A64

Signed saturating extract narrow.

SQXTN Bd,Hn

a → Hn

Bd → result

A64

Signed saturating extract narrow.

SQXTN Hd,Sn

a → Sn

Hd → result

A64

Signed saturating extract narrow.

SQXTN Sd,Dn

a → Dn

Sd → result

A64

Unsigned saturating extract narrow.

UQXTN Bd,Hn

a → Hn

Bd → result

A64

Unsigned saturating extract narrow.

UQXTN Hd,Sn

a → Sn

Hd → result

A64

Unsigned saturating extract narrow.

UQXTN Sd,Dn

a → Dn

Sd → result

A64

Signed saturating extract narrow.

SQXTN2 Vd.16B,Vn.8H

r → Vd.8B

a → Vn.8H

Vd.16B → result

A64

Signed saturating extract narrow.

SQXTN2 Vd.8H,Vn.4S

r → Vd.4H

a → Vn.4S

Vd.8H → result

A64

Signed saturating extract narrow.

SQXTN2 Vd.4S,Vn.2D

r → Vd.2S

a → Vn.2D

Vd.4S → result

A64

Unsigned saturating extract narrow.

UQXTN2 Vd.16B,Vn.8H

r → Vd.8B

a → Vn.8H

Vd.16B → result

A64

Unsigned saturating extract narrow.

UQXTN2 Vd.8H,Vn.4S

r → Vd.4H

a → Vn.4S

Vd.8H → result

A64

Unsigned saturating extract narrow.

UQXTN2 Vd.4S,Vn.2D

r → Vd.2S

a → Vn.2D

Vd.4S → result

A64

Signed saturating extract unsigned narrow.

SQXTUN Vd.8B,Vn.8H

a → Vn.8H

Vd.8B → result

v7/A32/A64

Signed saturating extract unsigned narrow.

SQXTUN Vd.4H,Vn.4S

a → Vn.4S

Vd.4H → result

v7/A32/A64

Signed saturating extract unsigned narrow.

SQXTUN Vd.2S,Vn.2D

a → Vn.2D

Vd.2S → result

v7/A32/A64

Signed saturating extract unsigned narrow.

SQXTUN Bd,Hn

a → Hn

Bd → result

A64

Signed saturating extract unsigned narrow.

SQXTUN Hd,Sn

a → Sn

Hd → result

A64

Signed saturating extract unsigned narrow.

SQXTUN Sd,Dn

a → Dn

Sd → result

A64

Signed saturating extract unsigned narrow.

SQXTUN2 Vd.16B,Vn.8H

r → Vd.8B

a → Vn.8H

Vd.16B → result

A64

Signed saturating extract unsigned narrow.

SQXTUN2 Vd.8H,Vn.4S

r → Vd.4H

a → Vn.4S

Vd.8H → result

A64

Signed saturating extract unsigned narrow.

SQXTUN2 Vd.4S,Vn.2D

r → Vd.2S

a → Vn.2D

Vd.4S → result

A64

Multiply-add to accumulator.

MLA Vd.4H,Vn.4H,Vm.H[lane]

a → Vd.4H

b → Vn.4H

v → Vm.4H

0 << lane << 3

Vd.4H → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.8H,Vn.8H,Vm.H[lane]

a → Vd.8H

b → Vn.8H

v → Vm.4H

0 << lane << 3

Vd.8H → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.2S,Vn.2S,Vm.S[lane]

a → Vd.2S

b → Vn.2S

v → Vm.2S

0 << lane << 1

Vd.2S → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.4S,Vn.4S,Vm.S[lane]

a → Vd.4S

b → Vn.4S

v → Vm.2S

0 << lane << 1

Vd.4S → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.4H,Vn.4H,Vm.H[lane]

a → Vd.4H

b → Vn.4H

v → Vm.4H

0 << lane << 3

Vd.4H → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.8H,Vn.8H,Vm.H[lane]

a → Vd.8H

b → Vn.8H

v → Vm.4H

0 << lane << 3

Vd.8H → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.2S,Vn.2S,Vm.S[lane]

a → Vd.2S

b → Vn.2S

v → Vm.2S

0 << lane << 1

Vd.2S → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.4S,Vn.4S,Vm.S[lane]

a → Vd.4S

b → Vn.4S

v → Vm.2S

0 << lane << 1

Vd.4S → result

v7/A32/A64

Undefined.

RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 1

0 << lane << 1

N/A → result

v7/A32/A64

Undefined.

RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 3

0 << lane << 1

N/A → result

v7/A32/A64

Multiply-add to accumulator.

MLA Vd.4H,Vn.4H,Vm.H[lane]

a → Vd.4H

b → Vn.4H

v → Vm.8H

0 << lane << 7

Vd.4H → result

A64

Multiply-add to accumulator.

MLA Vd.8H,Vn.8H,Vm.H[lane]

a → Vd.8H

b → Vn.8H

v → Vm.8H

0 << lane << 7

Vd.8H → result

A64

Multiply-add to accumulator.

MLA Vd.2S,Vn.2S,Vm.S[lane]

a → Vd.2S

b → Vn.2S

v → Vm.4S

0 << lane << 3

Vd.2S → result

A64

Multiply-add to accumulator.