NEON Intrinsics

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A64 Instruction

ADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

ADD Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

FADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FADD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FADD Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

ADD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

ADD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

SADDL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SADDL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SADDL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UADDL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UADDL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UADDL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SADDL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SADDL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SADDL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UADDL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

UADDL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UADDL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SADDW Vd.8H,Vn.8H,Vm.8B

Argument Preparation

a → Vn.8H 
b → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SADDW Vd.4S,Vn.4S,Vm.4H

Argument Preparation

a → Vn.4S 
b → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SADDW Vd.2D,Vn.2D,Vm.2S

Argument Preparation

a → Vn.2D 
b → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UADDW Vd.8H,Vn.8H,Vm.8B

Argument Preparation

a → Vn.8H 
b → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UADDW Vd.4S,Vn.4S,Vm.4H

Argument Preparation

a → Vn.4S 
b → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UADDW Vd.2D,Vn.2D,Vm.2S

Argument Preparation

a → Vn.2D 
b → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SADDW2 Vd.8H,Vn.8H,Vm.16B

Argument Preparation

a → Vn.8H 
b → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SADDW2 Vd.4S,Vn.4S,Vm.8H

Argument Preparation

a → Vn.4S 
b → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SADDW2 Vd.2D,Vn.2D,Vm.4S

Argument Preparation

a → Vn.2D 
b → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UADDW2 Vd.8H,Vn.8H,Vm.16B

Argument Preparation

a → Vn.8H 
b → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

UADDW2 Vd.4S,Vn.4S,Vm.8H

Argument Preparation

a → Vn.4S 
b → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UADDW2 Vd.2D,Vn.2D,Vm.4S

Argument Preparation

a → Vn.2D 
b → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SHADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SHADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SHADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SHADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SHADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SHADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UHADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

UHADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

UHADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

UHADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UHADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UHADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SRHADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SRHADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SRHADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SRHADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SRHADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SRHADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

URHADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

URHADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

URHADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

URHADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

URHADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

URHADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQADD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SQADD Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UQADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

UQADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

UQADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

UQADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UQADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UQADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UQADD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

UQADD Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQADD Bd,Bn,Bm

Argument Preparation

a → Bn 
b → Bm

Result

Bd → result

Supported architectures

A64

A64 Instruction

SQADD Hd,Hn,Hm

Argument Preparation

a → Hn 
b → Hm

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQADD Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQADD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

UQADD Bd,Bn,Bm

Argument Preparation

a → Bn 
b → Bm

Result

Bd → result

Supported architectures

A64

A64 Instruction

UQADD Hd,Hn,Hm

Argument Preparation

a → Hn 
b → Hm

Result

Hd → result

Supported architectures

A64

A64 Instruction

UQADD Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

UQADD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

SUQADD Vd.8B,Vn.8B

Argument Preparation

a → Vd.8B 
b → Vn.8B

Result

Vd.8B → result

Supported architectures

A64

A64 Instruction

SUQADD Vd.16B,Vn.16B

Argument Preparation

a → Vd.16B 
b → Vn.16B

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

SUQADD Vd.4H,Vn.4H

Argument Preparation

a → Vd.4H 
b → Vn.4H

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

SUQADD Vd.8H,Vn.8H

Argument Preparation

a → Vd.8H 
b → Vn.8H

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SUQADD Vd.2S,Vn.2S

Argument Preparation

a → Vd.2S 
b → Vn.2S

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

SUQADD Vd.4S,Vn.4S

Argument Preparation

a → Vd.4S 
b → Vn.4S

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SUQADD Dd,Dn

Argument Preparation

a → Dd 
b → Dn

Result

Dd → result

Supported architectures

A64

A64 Instruction

SUQADD Vd.2D,Vn.2D

Argument Preparation

a → Vd.2D 
b → Vn.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SUQADD Bd,Bn

Argument Preparation

a → Bd 
b → Bn

Result

Bd → result

Supported architectures

A64

A64 Instruction

SUQADD Hd,Hn

Argument Preparation

a → Hd 
b → Hn

Result

Hd → result

Supported architectures

A64

A64 Instruction

SUQADD Sd,Sn

Argument Preparation

a → Sd 
b → Sn

Result

Sd → result

Supported architectures

A64

A64 Instruction

SUQADD Dd,Dn

Argument Preparation

a → Dd 
b → Dn

Result

Dd → result

Supported architectures

A64

A64 Instruction

USQADD Vd.8B,Vn.8B

Argument Preparation

a → Vd.8B 
b → Vn.8B

Result

Vd.8B → result

Supported architectures

A64

A64 Instruction

USQADD Vd.16B,Vn.16B

Argument Preparation

a → Vd.16B 
b → Vn.16B

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

USQADD Vd.4H,Vn.4H

Argument Preparation

a → Vd.4H 
b → Vn.4H

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

USQADD Vd.8H,Vn.8H

Argument Preparation

a → Vd.8H 
b → Vn.8H

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

USQADD Vd.2S,Vn.2S

Argument Preparation

a → Vd.2S 
b → Vn.2S

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

USQADD Vd.4S,Vn.4S

Argument Preparation

a → Vd.4S 
b → Vn.4S

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

USQADD Dd,Dn

Argument Preparation

a → Dd 
b → Dn

Result

Dd → result

Supported architectures

A64

A64 Instruction

USQADD Vd.2D,Vn.2D

Argument Preparation

a → Vd.2D 
b → Vn.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

USQADD Bd,Bn

Argument Preparation

a → Bd 
b → Bn

Result

Bd → result

Supported architectures

A64

A64 Instruction

USQADD Hd,Hn

Argument Preparation

a → Hd 
b → Hn

Result

Hd → result

Supported architectures

A64

A64 Instruction

USQADD Sd,Sn

Argument Preparation

a → Sd 
b → Sn

Result

Sd → result

Supported architectures

A64

A64 Instruction

USQADD Dd,Dn

Argument Preparation

a → Dd 
b → Dn

Result

Dd → result

Supported architectures

A64

A64 Instruction

ADDHN Vd.8B,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

ADDHN Vd.4H,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

ADDHN Vd.2S,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

ADDHN Vd.8B,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

ADDHN Vd.4H,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

ADDHN Vd.2S,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

ADDHN2 Vd.16B,Vn.8H,Vm.8H

Argument Preparation

r → Vd.8B 
a → Vn.8H
b → Vm.8H

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

ADDHN2 Vd.8H,Vn.4S,Vm.4S

Argument Preparation

r → Vd.4H 
a → Vn.4S
b → Vm.4S

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

ADDHN2 Vd.4S,Vn.2D,Vm.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D
b → Vm.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

ADDHN2 Vd.16B,Vn.8H,Vm.8H

Argument Preparation

r → Vd.8B 
a → Vn.8H
b → Vm.8H

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

ADDHN2 Vd.8H,Vn.4S,Vm.4S

Argument Preparation

r → Vd.4H 
a → Vn.4S
b → Vm.4S

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

ADDHN2 Vd.4S,Vn.2D,Vm.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D
b → Vm.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

RADDHN Vd.8B,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

RADDHN Vd.4H,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

RADDHN Vd.2S,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

RADDHN Vd.8B,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

RADDHN Vd.4H,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

RADDHN Vd.2S,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

RADDHN2 Vd.16B,Vn.8H,Vm.8H

Argument Preparation

r → Vd.8B 
a → Vn.8H
b → Vm.8H

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

RADDHN2 Vd.8H,Vn.4S,Vm.4S

Argument Preparation

r → Vd.4H 
a → Vn.4S
b → Vm.4S

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

RADDHN2 Vd.4S,Vn.2D,Vm.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D
b → Vm.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

RADDHN2 Vd.16B,Vn.8H,Vm.8H

Argument Preparation

r → Vd.8B 
a → Vn.8H
b → Vm.8H

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

RADDHN2 Vd.8H,Vn.4S,Vm.4S

Argument Preparation

r → Vd.4H 
a → Vn.4S
b → Vm.4S

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

RADDHN2 Vd.4S,Vn.2D,Vm.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D
b → Vm.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

MUL Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMUL Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMUL Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

PMUL Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

PMUL Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

FMUL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMUL Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMULX Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FMULX Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FMULX Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMULX Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMULX Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

FMULX Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMULX Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.2S
0 << lane << 1

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FMULX Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.2S
0 << lane << 1

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dn 
v → Vm.1D
0 << lane << 0

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMULX Vd.2D,Vn.2D,Vm.D[lane]

Argument Preparation

a → Vn.2D 
v → Vm.1D
0 << lane << 0

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMULX Sd,Sn,Vm.S[lane]

Argument Preparation

a → Sn 
v → Vm.2S
0 << lane << 1

Result

Sd → result

Supported architectures

A64

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dn 
v → Vm.1D
0 << lane << 0

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMULX Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.4S
0 << lane << 3

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FMULX Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.4S
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dn 
v → Vm.2D
0 << lane << 1

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMULX Vd.2D,Vn.2D,Vm.D[lane]

Argument Preparation

a → Vn.2D 
v → Vm.2D
0 << lane << 1

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMULX Sd,Sn,Vm.S[lane]

Argument Preparation

a → Sn 
v → Vm.4S
0 << lane << 3

Result

Sd → result

Supported architectures

A64

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dn 
v → Vm.2D
0 << lane << 1

Result

Dd → result

Supported architectures

A64

A64 Instruction

FDIV Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FDIV Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FDIV Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FDIV Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

MLA Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8B 
b → Vn.8B
c → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vd.16B 
b → Vn.16B
c → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4H 
b → Vn.4H
c → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vd.8H 
b → Vn.8H
c → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2S 
b → Vn.2S
c → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vd.4S 
b → Vn.4S
c → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8B 
b → Vn.8B
c → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vd.16B 
b → Vn.16B
c → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4H 
b → Vn.4H
c → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vd.8H 
b → Vn.8H
c → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2S 
b → Vn.2S
c → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vd.4S 
b → Vn.4S
c → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

IGNORE

Argument Preparation

a → N/A 
b → N/A
c → N/A

Result

N/A → result

Supported architectures

v7/A32/A64

A64 Instruction

IGNORE

Argument Preparation

a → N/A 
b → N/A
c → N/A

Result

N/A → result

Supported architectures

v7/A32/A64

A64 Instruction

IGNORE

Argument Preparation

a → N/A 
b → N/A
c → N/A

Result

N/A → result

Supported architectures

A64

A64 Instruction

IGNORE

Argument Preparation

a → N/A 
b → N/A
c → N/A

Result

N/A → result

Supported architectures

A64

A64 Instruction

SMLAL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8H 
b → Vn.8B
c → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLAL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4S 
b → Vn.4H
c → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLAL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2D 
b → Vn.2S
c → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UMLAL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8H 
b → Vn.8B
c → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UMLAL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4S 
b → Vn.4H
c → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UMLAL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2D 
b → Vn.2S
c → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLAL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vd.8H 
b → Vn.16B
c → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SMLAL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vd.4S 
b → Vn.8H
c → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMLAL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vd.2D 
b → Vn.4S
c → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMLAL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vd.8H 
b → Vn.16B
c → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

UMLAL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vd.4S 
b → Vn.8H
c → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMLAL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vd.2D 
b → Vn.4S
c → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

MLS Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8B 
b → Vn.8B
c → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vd.16B 
b → Vn.16B
c → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4H 
b → Vn.4H
c → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vd.8H 
b → Vn.8H
c → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2S 
b → Vn.2S
c → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vd.4S 
b → Vn.4S
c → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8B 
b → Vn.8B
c → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vd.16B 
b → Vn.16B
c → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4H 
b → Vn.4H
c → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vd.8H 
b → Vn.8H
c → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2S 
b → Vn.2S
c → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vd.4S 
b → Vn.4S
c → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

IGNORE

Argument Preparation

a → N/A 
b → N/A
c → N/A

Result

N/A → result

Supported architectures

v7/A32/A64

A64 Instruction

IGNORE

Argument Preparation

a → N/A 
b → N/A
c → N/A

Result

N/A → result

Supported architectures

v7/A32/A64

A64 Instruction

IGNORE

Argument Preparation

a → N/A 
b → N/A
c → N/A

Result

N/A → result

Supported architectures

A64

A64 Instruction

IGNORE

Argument Preparation

a → N/A 
b → N/A
c → N/A

Result

N/A → result

Supported architectures

A64

A64 Instruction

SMLSL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8H 
b → Vn.8B
c → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLSL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4S 
b → Vn.4H
c → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLSL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2D 
b → Vn.2S
c → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UMLSL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8H 
b → Vn.8B
c → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UMLSL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4S 
b → Vn.4H
c → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UMLSL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2D 
b → Vn.2S
c → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLSL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vd.8H 
b → Vn.16B
c → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SMLSL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vd.4S 
b → Vn.8H
c → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMLSL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vd.2D 
b → Vn.4S
c → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMLSL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vd.8H 
b → Vn.16B
c → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

UMLSL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vd.4S 
b → Vn.8H
c → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMLSL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vd.2D 
b → Vn.4S
c → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMLA Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2S 
b → Vn.2S
c → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMLA Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vd.4S 
b → Vn.4S
c → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMADD Dd,Dn,Dm,Da

Argument Preparation

a → Da 
b → Dn
c → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMLA Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vd.2D 
b → Vn.2D
c → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMLA Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2S 
b → Vn.2S
v → Vm.2S
0 << lane << 1

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FMLA Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4S
v → Vm.2S
0 << lane << 1

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FMLA Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dd 
b → Dn
v → Vm.1D
0 << lane << 0

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMLA Vd.2D,Vn.2D,Vm.D[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2D
v → Vm.1D
0 << lane << 0

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMLA Sd,Sn,Vm.S[lane]

Argument Preparation

a → Sd 
b → Sn
v → Vm.2S
0 << lane << 1

Result

Sd → result

Supported architectures

A64

A64 Instruction

FMLA Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dd 
b → Dn
v → Vm.1D
0 << lane << 0

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMLA Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2S 
b → Vn.2S
v → Vm.4S
0 << lane << 3

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FMLA Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4S
v → Vm.4S
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FMLA Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dd 
b → Dn
v → Vm.2D
0 << lane << 1

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMLA Vd.2D,Vn.2D,Vm.D[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2D
v → Vm.2D
0 << lane << 1

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMLA Sd,Sn,Vm.S[lane]

Argument Preparation

a → Sd 
b → Sn
v → Vm.4S
0 << lane << 3

Result

Sd → result

Supported architectures

A64

A64 Instruction

FMLA Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dd 
b → Dn
v → Vm.2D
0 << lane << 1

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMLS Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2S 
b → Vn.2S
c → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMLS Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vd.4S 
b → Vn.4S
c → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMSUB Dd,Dn,Dm,Da

Argument Preparation

a → Da 
b → Dn
c → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMLS Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vd.2D 
b → Vn.2D
c → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMLS Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2S 
b → Vn.2S
v → Vm.2S
0 << lane << 1

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FMLS Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4S
v → Vm.2S
0 << lane << 1

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FMLS Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dd 
b → Dn
v → Vm.1D
0 << lane << 0

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMLS Vd.2D,Vn.2D,Vm.D[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2D
v → Vm.1D
0 << lane << 0

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMLS Sd,Sn,Vm.S[lane]

Argument Preparation

a → Sd 
b → Sn
v → Vm.2S
0 << lane << 1

Result

Sd → result

Supported architectures

A64

A64 Instruction

FMLS Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dd 
b → Dn
v → Vm.1D
0 << lane << 0

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMLS Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2S 
b → Vn.2S
v → Vm.4S
0 << lane << 3

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FMLS Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4S
v → Vm.4S
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FMLS Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dd 
b → Dn
v → Vm.2D
0 << lane << 1

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMLS Vd.2D,Vn.2D,Vm.D[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2D
v → Vm.2D
0 << lane << 1

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMLS Sd,Sn,Vm.S[lane]

Argument Preparation

a → Sd 
b → Sn
v → Vm.4S
0 << lane << 3

Result

Sd → result

Supported architectures

A64

A64 Instruction

FMLS Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dd 
b → Dn
v → Vm.2D
0 << lane << 1

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQDMULH Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULH Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULH Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULH Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULH Hd,Hn,Hm

Argument Preparation

a → Hn 
b → Hm

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQDMULH Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQRDMULH Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRDMULH Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRDMULH Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRDMULH Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRDMULH Hd,Hn,Hm

Argument Preparation

a → Hn 
b → Hm

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQRDMULH Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQDMLAL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4S 
b → Vn.4H
c → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMLAL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2D 
b → Vn.2S
c → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMLAL Sd,Hn,Hm

Argument Preparation

a → Sd 
b → Hn
c → Hm

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQDMLAL Dd,Sn,Sm

Argument Preparation

a → Dd 
b → Sn
c → Sm

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQDMLAL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vd.4S 
b → Vn.8H
c → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMLAL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vd.2D 
b → Vn.4S
c → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQDMLSL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4S 
b → Vn.4H
c → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMLSL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2D 
b → Vn.2S
c → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMLSL Sd,Hn,Hm

Argument Preparation

a → Sd 
b → Hn
c → Hm

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQDMLSL Dd,Sn,Sm

Argument Preparation

a → Dd 
b → Sn
c → Sm

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQDMLSL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vd.4S 
b → Vn.8H
c → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMLSL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vd.2D 
b → Vn.4S
c → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SMULL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SMULL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SMULL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UMULL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UMULL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UMULL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

PMULL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SMULL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SMULL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMULL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMULL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

UMULL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMULL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

PMULL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SQDMULL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULL Sd,Hn,Hm

Argument Preparation

a → Hn 
b → Hm

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQDMULL Dd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQDMULL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMULL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SUB Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SUB Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

FSUB Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FSUB Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FSUB Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FSUB Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SUB Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

SUB Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

SSUBL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SSUBL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SSUBL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

USUBL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

USUBL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

USUBL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SSUBL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SSUBL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SSUBL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

USUBL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

USUBL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

USUBL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SSUBW Vd.8H,Vn.8H,Vm.8B

Argument Preparation

a → Vn.8H 
b → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SSUBW Vd.4S,Vn.4S,Vm.4H

Argument Preparation

a → Vn.4S 
b → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SSUBW Vd.2D,Vn.2D,Vm.2S

Argument Preparation

a → Vn.2D 
b → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

USUBW Vd.8H,Vn.8H,Vm.8B

Argument Preparation

a → Vn.8H 
b → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

USUBW Vd.4S,Vn.4S,Vm.4H

Argument Preparation

a → Vn.4S 
b → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

USUBW Vd.2D,Vn.2D,Vm.2S

Argument Preparation

a → Vn.2D 
b → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SSUBW2 Vd.8H,Vn.8H,Vm.16B

Argument Preparation

a → Vn.8H 
b → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SSUBW2 Vd.4S,Vn.4S,Vm.8H

Argument Preparation

a → Vn.4S 
b → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SSUBW2 Vd.2D,Vn.2D,Vm.4S

Argument Preparation

a → Vn.2D 
b → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

USUBW2 Vd.8H,Vn.8H,Vm.16B

Argument Preparation

a → Vn.8H 
b → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

USUBW2 Vd.4S,Vn.4S,Vm.8H

Argument Preparation

a → Vn.4S 
b → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

USUBW2 Vd.2D,Vn.2D,Vm.4S

Argument Preparation

a → Vn.2D 
b → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SHSUB Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SHSUB Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SHSUB Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SHSUB Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SHSUB Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SHSUB Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UHSUB Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

UHSUB Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

UHSUB Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

UHSUB Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UHSUB Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UHSUB Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSUB Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSUB Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSUB Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSUB Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSUB Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSUB Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSUB Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSUB Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSUB Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSUB Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSUB Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSUB Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSUB Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSUB Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSUB Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSUB Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSUB Bd,Bn,Bm

Argument Preparation

a → Bn 
b → Bm

Result

Bd → result

Supported architectures

A64

A64 Instruction

SQSUB Hd,Hn,Hm

Argument Preparation

a → Hn 
b → Hm

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQSUB Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQSUB Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

UQSUB Bd,Bn,Bm

Argument Preparation

a → Bn 
b → Bm

Result

Bd → result

Supported architectures

A64

A64 Instruction

UQSUB Hd,Hn,Hm

Argument Preparation

a → Hn 
b → Hm

Result

Hd → result

Supported architectures

A64

A64 Instruction

UQSUB Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

UQSUB Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

SUBHN Vd.8B,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SUBHN Vd.4H,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SUBHN Vd.2S,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SUBHN Vd.8B,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SUBHN Vd.4H,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SUBHN Vd.2S,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SUBHN2 Vd.16B,Vn.8H,Vm.8H

Argument Preparation

r → Vd.8B 
a → Vn.8H
b → Vm.8H

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

SUBHN2 Vd.8H,Vn.4S,Vm.4S

Argument Preparation

r → Vd.4H 
a → Vn.4S
b → Vm.4S

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SUBHN2 Vd.4S,Vn.2D,Vm.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D
b → Vm.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SUBHN2 Vd.16B,Vn.8H,Vm.8H

Argument Preparation

r → Vd.8B 
a → Vn.8H
b → Vm.8H

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

SUBHN2 Vd.8H,Vn.4S,Vm.4S

Argument Preparation

r → Vd.4H 
a → Vn.4S
b → Vm.4S

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SUBHN2 Vd.4S,Vn.2D,Vm.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D
b → Vm.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

RSUBHN Vd.8B,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

RSUBHN Vd.4H,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

RSUBHN Vd.2S,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

RSUBHN Vd.8B,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

RSUBHN Vd.4H,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

RSUBHN Vd.2S,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

RSUBHN2 Vd.16B,Vn.8H,Vm.8H

Argument Preparation

r → Vd.8B 
a → Vn.8H
b → Vm.8H

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

RSUBHN2 Vd.8H,Vn.4S,Vm.4S

Argument Preparation

r → Vd.4H 
a → Vn.4S
b → Vm.4S

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

RSUBHN2 Vd.4S,Vn.2D,Vm.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D
b → Vm.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

RSUBHN2 Vd.16B,Vn.8H,Vm.8H

Argument Preparation

r → Vd.8B 
a → Vn.8H
b → Vm.8H

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

RSUBHN2 Vd.8H,Vn.4S,Vm.4S

Argument Preparation

r → Vd.4H 
a → Vn.4S
b → Vm.4S

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

RSUBHN2 Vd.4S,Vn.2D,Vm.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D
b → Vm.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMEQ Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMEQ Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMEQ Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMEQ Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMEQ Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMEQ Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMEQ Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMEQ Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMEQ Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMEQ Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMEQ Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCMEQ Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCMEQ Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMEQ Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMEQ Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMEQ Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMEQ Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMEQ Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A32/A64

A64 Instruction

CMEQ Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A32/A64

A64 Instruction

FCMEQ Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMEQ Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMEQ Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMEQ Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMEQ Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCMEQ Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.8B,Vn.8B,#0

Argument Preparation

a → Vn.8B 

Result

Vd.8B → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.16B,Vn.16B,#0

Argument Preparation

a → Vn.16B 

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.4H,Vn.4H,#0

Argument Preparation

a → Vn.4H 

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.8H,Vn.8H,#0

Argument Preparation

a → Vn.8H 

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.2S,Vn.2S,#0

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.4S,Vn.4S,#0

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.8B,Vn.8B,#0

Argument Preparation

a → Vn.8B 

Result

Vd.8B → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.16B,Vn.16B,#0

Argument Preparation

a → Vn.16B 

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.4H,Vn.4H,#0

Argument Preparation

a → Vn.4H 

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.8H,Vn.8H,#0

Argument Preparation

a → Vn.8H 

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.2S,Vn.2S,#0

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.4S,Vn.4S,#0

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FCMEQ Vd.2S,Vn.2S,#0

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FCMEQ Vd.4S,Vn.4S,#0

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.8B,Vn.8B,#0

Argument Preparation

a → Vn.8B 

Result

Vd.8B → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.16B,Vn.16B,#0

Argument Preparation

a → Vn.16B 

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

CMEQ Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.2D,Vn.2D,#0

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMEQ Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMEQ Vd.2D,Vn.2D,#0

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMEQ Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A32/A64

A64 Instruction

CMEQ Vd.2D,Vn.2D,#0

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A32/A64

A64 Instruction

FCMEQ Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMEQ Vd.2D,Vn.2D,#0

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMEQ Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMEQ Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMEQ Sd,Sn,#0

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCMEQ Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMGE Vd.8B,Vm.8B,Vn.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGE Vd.16B,Vm.16B,Vn.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGE Vd.4H,Vm.4H,Vn.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGE Vd.8H,Vm.8H,Vn.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGE Vd.2S,Vm.2S,Vn.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGE Vd.4S,Vm.4S,Vn.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHS Vd.8B,Vm.8B,Vn.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHS Vd.16B,Vm.16B,Vn.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHS Vd.4H,Vm.4H,Vn.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHS Vd.8H,Vm.8H,Vn.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHS Vd.2S,Vm.2S,Vn.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHS Vd.4S,Vm.4S,Vn.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCMGE Vd.2S,Vm.2S,Vn.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCMGE Vd.4S,Vm.4S,Vn.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGE Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMGE Vd.2D,Vm.2D,Vn.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMHS Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMHS Vd.2D,Vm.2D,Vn.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCMGE Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMGE Vd.2D,Vm.2D,Vn.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMGE Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMHS Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMGE Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCMGE Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMGE Vd.8B,Vn.8B,#0

Argument Preparation

a → Vn.8B 

Result

Vd.8B → result

Supported architectures

A64

A64 Instruction

CMGE Vd.16B,Vn.16B,#0

Argument Preparation

a → Vn.16B 

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

CMGE Vd.4H,Vn.4H,#0

Argument Preparation

a → Vn.4H 

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

CMGE Vd.8H,Vn.8H,#0

Argument Preparation

a → Vn.8H 

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

CMGE Vd.2S,Vn.2S,#0

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

CMGE Vd.4S,Vn.4S,#0

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

CMGE Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMGE Vd.2D,Vn.2D,#0

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCMGE Vd.2S,Vn.2S,#0

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FCMGE Vd.4S,Vn.4S,#0

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FCMGE Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMGE Vd.2D,Vn.2D,#0

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMGE Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMGE Sd,Sn,#0

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCMGE Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMGE Vd.8B,Vm.8B,Vn.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGE Vd.16B,Vm.16B,Vn.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGE Vd.4H,Vm.4H,Vn.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGE Vd.8H,Vm.8H,Vn.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGE Vd.2S,Vm.2S,Vn.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGE Vd.4S,Vm.4S,Vn.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHS Vd.8B,Vm.8B,Vn.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHS Vd.16B,Vm.16B,Vn.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHS Vd.4H,Vm.4H,Vn.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHS Vd.8H,Vm.8H,Vn.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHS Vd.2S,Vm.2S,Vn.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHS Vd.4S,Vm.4S,Vn.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCMGE Vd.2S,Vm.2S,Vn.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCMGE Vd.4S,Vm.4S,Vn.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGE Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMGE Vd.2D,Vm.2D,Vn.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMHS Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMHS Vd.2D,Vm.2D,Vn.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCMGE Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMGE Vd.2D,Vm.2D,Vn.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMGE Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMHS Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMGE Sd,Sm,Sn

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCMGE Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMLE Vd.8B,Vn.8B,#0

Argument Preparation

a → Vn.8B 

Result

Vd.8B → result

Supported architectures

A64

A64 Instruction

CMLE Vd.16B,Vn.16B,#0

Argument Preparation

a → Vn.16B 

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

CMLE Vd.4H,Vn.4H,#0

Argument Preparation

a → Vn.4H 

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

CMLE Vd.8H,Vn.8H,#0

Argument Preparation

a → Vn.8H 

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

CMLE Vd.2S,Vn.2S,#0

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

CMLE Vd.4S,Vn.4S,#0

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

CMLE Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMLE Vd.2D,Vn.2D,#0

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMLE Vd.2S,Vn.2S,#0

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FCMLE Vd.4S,Vn.4S,#0

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FCMLE Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMLE Vd.2D,Vn.2D,#0

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMLE Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMLE Sd,Sn,#0

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCMLE Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMGT Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGT Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGT Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGT Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGT Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGT Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHI Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHI Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHI Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHI Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHI Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHI Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCMGT Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCMGT Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGT Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMGT Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMHI Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMHI Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCMGT Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMGT Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMGT Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMHI Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMGT Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCMGT Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMGT Vd.8B,Vn.8B,#0

Argument Preparation

a → Vn.8B 

Result

Vd.8B → result

Supported architectures

A64

A64 Instruction

CMGT Vd.16B,Vn.16B,#0

Argument Preparation

a → Vn.16B 

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

CMGT Vd.4H,Vn.4H,#0

Argument Preparation

a → Vn.4H 

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

CMGT Vd.8H,Vn.8H,#0

Argument Preparation

a → Vn.8H 

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

CMGT Vd.2S,Vn.2S,#0

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

CMGT Vd.4S,Vn.4S,#0

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

CMGT Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMGT Vd.2D,Vn.2D,#0

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCMGT Vd.2S,Vn.2S,#0

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FCMGT Vd.4S,Vn.4S,#0

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FCMGT Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMGT Vd.2D,Vn.2D,#0

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMGT Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMGT Sd,Sn,#0

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCMGT Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMGT Vd.8B,Vm.8B,Vn.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGT Vd.16B,Vm.16B,Vn.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGT Vd.4H,Vm.4H,Vn.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGT Vd.8H,Vm.8H,Vn.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGT Vd.2S,Vm.2S,Vn.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGT Vd.4S,Vm.4S,Vn.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHI Vd.8B,Vm.8B,Vn.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHI Vd.16B,Vm.16B,Vn.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHI Vd.4H,Vm.4H,Vn.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHI Vd.8H,Vm.8H,Vn.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHI Vd.2S,Vm.2S,Vn.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMHI Vd.4S,Vm.4S,Vn.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCMGT Vd.2S,Vm.2S,Vn.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCMGT Vd.4S,Vm.4S,Vn.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMGT Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMGT Vd.2D,Vm.2D,Vn.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMHI Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMHI Vd.2D,Vm.2D,Vn.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCMGT Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMGT Vd.2D,Vm.2D,Vn.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMGT Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMHI Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMGT Sd,Sm,Sn

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCMGT Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMLT Vd.8B,Vn.8B,#0

Argument Preparation

a → Vn.8B 

Result

Vd.8B → result

Supported architectures

A64

A64 Instruction

CMLT Vd.16B,Vn.16B,#0

Argument Preparation

a → Vn.16B 

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

CMLT Vd.4H,Vn.4H,#0

Argument Preparation

a → Vn.4H 

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

CMLT Vd.8H,Vn.8H,#0

Argument Preparation

a → Vn.8H 

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

CMLT Vd.2S,Vn.2S,#0

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

CMLT Vd.4S,Vn.4S,#0

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

CMLT Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMLT Vd.2D,Vn.2D,#0

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCMLT Vd.2S,Vn.2S,#0

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FCMLT Vd.4S,Vn.4S,#0

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FCMLT Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMLT Vd.2D,Vn.2D,#0

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMLT Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCMLT Sd,Sn,#0

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCMLT Dd,Dn,#0

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FACGE Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FACGE Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FACGE Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FACGE Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FACGE Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

FACGE Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FACGE Vd.2S,Vm.2S,Vn.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FACGE Vd.4S,Vm.4S,Vn.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FACGE Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FACGE Vd.2D,Vm.2D,Vn.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FACGE Sd,Sm,Sn

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

FACGE Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FACGT Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FACGT Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FACGT Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FACGT Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FACGT Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

FACGT Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FACGT Vd.2S,Vm.2S,Vn.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FACGT Vd.4S,Vm.4S,Vn.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FACGT Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FACGT Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FACGT Sd,Sm,Sn

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

FACGT Dd,Dm,Dn

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMTST Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMTST Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMTST Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMTST Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMTST Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMTST Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMTST Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMTST Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMTST Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMTST Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

CMTST Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMTST Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

CMTST Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMTST Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CMTST Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMTST Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMTST Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMTST Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

CMTST Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A32/A64

A64 Instruction

CMTST Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A32/A64

A64 Instruction

CMTST Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

CMTST Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

SABD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SABD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SABD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SABD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SABD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SABD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UABD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

UABD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

UABD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

UABD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UABD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UABD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FABD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FABD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FABD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FABD Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FABD Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

FABD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

SABDL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SABDL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SABDL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UABDL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UABDL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UABDL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SABDL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SABDL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SABDL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UABDL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

UABDL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UABDL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SABA Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8B 
b → Vn.8B
c → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SABA Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vd.16B 
b → Vn.16B
c → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SABA Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4H 
b → Vn.4H
c → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SABA Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vd.8H 
b → Vn.8H
c → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SABA Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2S 
b → Vn.2S
c → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SABA Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vd.4S 
b → Vn.4S
c → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UABA Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8B 
b → Vn.8B
c → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

UABA Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vd.16B 
b → Vn.16B
c → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

UABA Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4H 
b → Vn.4H
c → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

UABA Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vd.8H 
b → Vn.8H
c → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UABA Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2S 
b → Vn.2S
c → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UABA Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vd.4S 
b → Vn.4S
c → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SABAL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8H 
b → Vn.8B
c → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SABAL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4S 
b → Vn.4H
c → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SABAL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2D 
b → Vn.2S
c → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UABAL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8H 
b → Vn.8B
c → Vm.8B

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UABAL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4S 
b → Vn.4H
c → Vm.4H

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UABAL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2D 
b → Vn.2S
c → Vm.2S

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SABAL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vd.8H 
b → Vn.16B
c → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SABAL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vd.4S 
b → Vn.8H
c → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SABAL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vd.2D 
b → Vn.4S
c → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UABAL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vd.8H 
b → Vn.16B
c → Vm.16B

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

UABAL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vd.4S 
b → Vn.8H
c → Vm.8H

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UABAL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vd.2D 
b → Vn.4S
c → Vm.4S

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SMAX Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SMAX Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SMAX Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SMAX Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SMAX Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SMAX Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UMAX Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

UMAX Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

UMAX Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

UMAX Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UMAX Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UMAX Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMAX Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMAX Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMAX Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMAX Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SMIN Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SMIN Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SMIN Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SMIN Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SMIN Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SMIN Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UMIN Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

UMIN Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

UMIN Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

UMIN Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UMIN Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UMIN Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMIN Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMIN Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMIN Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMIN Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMAXNM Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FMAXNM Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FMAXNM Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMAXNM Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMINNM Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FMINNM Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FMINNM Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMINNM Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SSHL Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHL Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHL Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHL Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHL Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHL Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHL Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

USHL Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

USHL Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

USHL Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

USHL Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

USHL Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

USHL Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

USHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

USHL Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

USHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQSHL Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Bd,Bn,Bm

Argument Preparation

a → Bn 
b → Bm

Result

Bd → result

Supported architectures

A64

A64 Instruction

SQSHL Hd,Hn,Hm

Argument Preparation

a → Hn 
b → Hm

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQSHL Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQSHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

UQSHL Bd,Bn,Bm

Argument Preparation

a → Bn 
b → Bm

Result

Bd → result

Supported architectures

A64

A64 Instruction

UQSHL Hd,Hn,Hm

Argument Preparation

a → Hn 
b → Hm

Result

Hd → result

Supported architectures

A64

A64 Instruction

UQSHL Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

UQSHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

SRSHL Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHL Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHL Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHL Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHL Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHL Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHL Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHL Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHL Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHL Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHL Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHL Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHL Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHL Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

URSHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQRSHL Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRSHL Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRSHL Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRSHL Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRSHL Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRSHL Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRSHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRSHL Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UQRSHL Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

UQRSHL Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

UQRSHL Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

UQRSHL Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UQRSHL Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UQRSHL Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UQRSHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

UQRSHL Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRSHL Bd,Bn,Bm

Argument Preparation

a → Bn 
b → Bm

Result

Bd → result

Supported architectures

A64

A64 Instruction

SQRSHL Hd,Hn,Hm

Argument Preparation

a → Hn 
b → Hm

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQRSHL Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQRSHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

UQRSHL Bd,Bn,Bm

Argument Preparation

a → Bn 
b → Bm

Result

Bd → result

Supported architectures

A64

A64 Instruction

UQRSHL Hd,Hn,Hm

Argument Preparation

a → Hn 
b → Hm

Result

Hd → result

Supported architectures

A64

A64 Instruction

UQRSHL Sd,Sn,Sm

Argument Preparation

a → Sn 
b → Sm

Result

Sd → result

Supported architectures

A64

A64 Instruction

UQRSHL Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Result

Dd → result

Supported architectures

A64

A64 Instruction

SSHR Vd.8B,Vn.8B,#n

Argument Preparation

a → Vn.8B 
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHR Vd.16B,Vn.16B,#n

Argument Preparation

a → Vn.16B 
1 << n << 8

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHR Vd.4H,Vn.4H,#n

Argument Preparation

a → Vn.4H 
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHR Vd.8H,Vn.8H,#n

Argument Preparation

a → Vn.8H 
1 << n << 16

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHR Vd.2S,Vn.2S,#n

Argument Preparation

a → Vn.2S 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHR Vd.4S,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 32

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHR Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHR Vd.2D,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 64

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

USHR Vd.8B,Vn.8B,#n

Argument Preparation

a → Vn.8B 
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

USHR Vd.16B,Vn.16B,#n

Argument Preparation

a → Vn.16B 
1 << n << 8

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

USHR Vd.4H,Vn.4H,#n

Argument Preparation

a → Vn.4H 
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

USHR Vd.8H,Vn.8H,#n

Argument Preparation

a → Vn.8H 
1 << n << 16

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

USHR Vd.2S,Vn.2S,#n

Argument Preparation

a → Vn.2S 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

USHR Vd.4S,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 32

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

USHR Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

USHR Vd.2D,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 64

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHR Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

USHR Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

SHL Vd.8B,Vn.8B,#n

Argument Preparation

a → Vn.8B 
0 << n << 7

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Vd.16B,Vn.16B,#n

Argument Preparation

a → Vn.16B 
0 << n << 7

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Vd.4H,Vn.4H,#n

Argument Preparation

a → Vn.4H 
0 << n << 15

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Vd.8H,Vn.8H,#n

Argument Preparation

a → Vn.8H 
0 << n << 15

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Vd.2S,Vn.2S,#n

Argument Preparation

a → Vn.2S 
0 << n << 31

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Vd.4S,Vn.4S,#n

Argument Preparation

a → Vn.4S 
0 << n << 31

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Dd,Dn,#n

Argument Preparation

a → Dn 
0 << n << 63

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Vd.2D,Vn.2D,#n

Argument Preparation

a → Vn.2D 
0 << n << 63

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Vd.8B,Vn.8B,#n

Argument Preparation

a → Vn.8B 
0 << n << 7

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Vd.16B,Vn.16B,#n

Argument Preparation

a → Vn.16B 
0 << n << 7

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Vd.4H,Vn.4H,#n

Argument Preparation

a → Vn.4H 
0 << n << 15

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Vd.8H,Vn.8H,#n

Argument Preparation

a → Vn.8H 
0 << n << 15

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Vd.2S,Vn.2S,#n

Argument Preparation

a → Vn.2S 
0 << n << 31

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Vd.4S,Vn.4S,#n

Argument Preparation

a → Vn.4S 
0 << n << 31

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Dd,Dn,#n

Argument Preparation

a → Dn 
0 << n << 63

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Vd.2D,Vn.2D,#n

Argument Preparation

a → Vn.2D 
0 << n << 63

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SHL Dd,Dn,#n

Argument Preparation

a → Dn 
0 << n << 63

Result

Dd → result

Supported architectures

A64

A64 Instruction

SHL Dd,Dn,#n

Argument Preparation

a → Dn 
0 << n << 63

Result

Dd → result

Supported architectures

A64

A64 Instruction

SRSHR Vd.8B,Vn.8B,#n

Argument Preparation

a → Vn.8B 
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHR Vd.16B,Vn.16B,#n

Argument Preparation

a → Vn.16B 
1 << n << 8

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHR Vd.4H,Vn.4H,#n

Argument Preparation

a → Vn.4H 
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHR Vd.8H,Vn.8H,#n

Argument Preparation

a → Vn.8H 
1 << n << 16

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHR Vd.2S,Vn.2S,#n

Argument Preparation

a → Vn.2S 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHR Vd.4S,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 32

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHR Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHR Vd.2D,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 64

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHR Vd.8B,Vn.8B,#n

Argument Preparation

a → Vn.8B 
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHR Vd.16B,Vn.16B,#n

Argument Preparation

a → Vn.16B 
1 << n << 8

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHR Vd.4H,Vn.4H,#n

Argument Preparation

a → Vn.4H 
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHR Vd.8H,Vn.8H,#n

Argument Preparation

a → Vn.8H 
1 << n << 16

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHR Vd.2S,Vn.2S,#n

Argument Preparation

a → Vn.2S 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHR Vd.4S,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 32

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHR Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

URSHR Vd.2D,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 64

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSHR Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

URSHR Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

SSRA Vd.8B,Vn.8B,#n

Argument Preparation

a → Vd.8B 
b → Vn.8B
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SSRA Vd.16B,Vn.16B,#n

Argument Preparation

a → Vd.16B 
b → Vn.16B
1 << n << 8

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SSRA Vd.4H,Vn.4H,#n

Argument Preparation

a → Vd.4H 
b → Vn.4H
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SSRA Vd.8H,Vn.8H,#n

Argument Preparation

a → Vd.8H 
b → Vn.8H
1 << n << 16

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SSRA Vd.2S,Vn.2S,#n

Argument Preparation

a → Vd.2S 
b → Vn.2S
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SSRA Vd.4S,Vn.4S,#n

Argument Preparation

a → Vd.4S 
b → Vn.4S
1 << n << 32

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SSRA Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
1 << n << 64

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SSRA Vd.2D,Vn.2D,#n

Argument Preparation

a → Vd.2D 
b → Vn.2D
1 << n << 64

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

USRA Vd.8B,Vn.8B,#n

Argument Preparation

a → Vd.8B 
b → Vn.8B
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

USRA Vd.16B,Vn.16B,#n

Argument Preparation

a → Vd.16B 
b → Vn.16B
1 << n << 8

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

USRA Vd.4H,Vn.4H,#n

Argument Preparation

a → Vd.4H 
b → Vn.4H
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

USRA Vd.8H,Vn.8H,#n

Argument Preparation

a → Vd.8H 
b → Vn.8H
1 << n << 16

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

USRA Vd.2S,Vn.2S,#n

Argument Preparation

a → Vd.2S 
b → Vn.2S
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

USRA Vd.4S,Vn.4S,#n

Argument Preparation

a → Vd.4S 
b → Vn.4S
1 << n << 32

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

USRA Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
1 << n << 64

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

USRA Vd.2D,Vn.2D,#n

Argument Preparation

a → Vd.2D 
b → Vn.2D
1 << n << 64

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SSRA Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

USRA Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

SRSRA Vd.8B,Vn.8B,#n

Argument Preparation

a → Vd.8B 
b → Vn.8B
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSRA Vd.16B,Vn.16B,#n

Argument Preparation

a → Vd.16B 
b → Vn.16B
1 << n << 8

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSRA Vd.4H,Vn.4H,#n

Argument Preparation

a → Vd.4H 
b → Vn.4H
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSRA Vd.8H,Vn.8H,#n

Argument Preparation

a → Vd.8H 
b → Vn.8H
1 << n << 16

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSRA Vd.2S,Vn.2S,#n

Argument Preparation

a → Vd.2S 
b → Vn.2S
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSRA Vd.4S,Vn.4S,#n

Argument Preparation

a → Vd.4S 
b → Vn.4S
1 << n << 32

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSRA Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
1 << n << 64

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSRA Vd.2D,Vn.2D,#n

Argument Preparation

a → Vd.2D 
b → Vn.2D
1 << n << 64

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

URSRA Vd.8B,Vn.8B,#n

Argument Preparation

a → Vd.8B 
b → Vn.8B
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

URSRA Vd.16B,Vn.16B,#n

Argument Preparation

a → Vd.16B 
b → Vn.16B
1 << n << 8

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

URSRA Vd.4H,Vn.4H,#n

Argument Preparation

a → Vd.4H 
b → Vn.4H
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

URSRA Vd.8H,Vn.8H,#n

Argument Preparation

a → Vd.8H 
b → Vn.8H
1 << n << 16

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

URSRA Vd.2S,Vn.2S,#n

Argument Preparation

a → Vd.2S 
b → Vn.2S
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

URSRA Vd.4S,Vn.4S,#n

Argument Preparation

a → Vd.4S 
b → Vn.4S
1 << n << 32

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

URSRA Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
1 << n << 64

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

URSRA Vd.2D,Vn.2D,#n

Argument Preparation

a → Vd.2D 
b → Vn.2D
1 << n << 64

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SRSRA Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

URSRA Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQSHL Vd.8B,Vn.8B,#n

Argument Preparation

a → Vn.8B 
0 << n << 7

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Vd.16B,Vn.16B,#n

Argument Preparation

a → Vn.16B 
0 << n << 7

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Vd.4H,Vn.4H,#n

Argument Preparation

a → Vn.4H 
0 << n << 15

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Vd.8H,Vn.8H,#n

Argument Preparation

a → Vn.8H 
0 << n << 15

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Vd.2S,Vn.2S,#n

Argument Preparation

a → Vn.2S 
0 << n << 31

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Vd.4S,Vn.4S,#n

Argument Preparation

a → Vn.4S 
0 << n << 31

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Dd,Dn,#n

Argument Preparation

a → Dn 
0 << n << 63

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Vd.2D,Vn.2D,#n

Argument Preparation

a → Vn.2D 
0 << n << 63

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Vd.8B,Vn.8B,#n

Argument Preparation

a → Vn.8B 
0 << n << 7

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Vd.16B,Vn.16B,#n

Argument Preparation

a → Vn.16B 
0 << n << 7

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Vd.4H,Vn.4H,#n

Argument Preparation

a → Vn.4H 
0 << n << 15

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Vd.8H,Vn.8H,#n

Argument Preparation

a → Vn.8H 
0 << n << 15

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Vd.2S,Vn.2S,#n

Argument Preparation

a → Vn.2S 
0 << n << 31

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Vd.4S,Vn.4S,#n

Argument Preparation

a → Vn.4S 
0 << n << 31

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Dd,Dn,#n

Argument Preparation

a → Dn 
0 << n << 63

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHL Vd.2D,Vn.2D,#n

Argument Preparation

a → Vn.2D 
0 << n << 63

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHL Bd,Bn,#n

Argument Preparation

a → Bn 
0 << n << 7

Result

Bd → result

Supported architectures

A64

A64 Instruction

SQSHL Hd,Hn,#n

Argument Preparation

a → Hn 
0 << n << 15

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQSHL Sd,Sn,#n

Argument Preparation

a → Sn 
0 << n << 31

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQSHL Dd,Dn,#n

Argument Preparation

a → Dn 
0 << n << 63

Result

Dd → result

Supported architectures

A64

A64 Instruction

UQSHL Bd,Bn,#n

Argument Preparation

a → Bn 
0 << n << 7

Result

Bd → result

Supported architectures

A64

A64 Instruction

UQSHL Hd,Hn,#n

Argument Preparation

a → Hn 
0 << n << 15

Result

Hd → result

Supported architectures

A64

A64 Instruction

UQSHL Sd,Sn,#n

Argument Preparation

a → Sn 
0 << n << 31

Result

Sd → result

Supported architectures

A64

A64 Instruction

UQSHL Dd,Dn,#n

Argument Preparation

a → Dn 
0 << n << 63

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQSHLU Vd.8B,Vn.8B,#n

Argument Preparation

a → Vn.8B 
0 << n << 7

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHLU Vd.16B,Vn.16B,#n

Argument Preparation

a → Vn.16B 
0 << n << 7

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHLU Vd.4H,Vn.4H,#n

Argument Preparation

a → Vn.4H 
0 << n << 15

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHLU Vd.8H,Vn.8H,#n

Argument Preparation

a → Vn.8H 
0 << n << 15

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHLU Vd.2S,Vn.2S,#n

Argument Preparation

a → Vn.2S 
0 << n << 31

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHLU Vd.4S,Vn.4S,#n

Argument Preparation

a → Vn.4S 
0 << n << 31

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHLU Dd,Dn,#n

Argument Preparation

a → Dn 
0 << n << 63

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHLU Vd.2D,Vn.2D,#n

Argument Preparation

a → Vn.2D 
0 << n << 63

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHLU Bd,Bn,#n

Argument Preparation

a → Bn 
0 << n << 7

Result

Bd → result

Supported architectures

A64

A64 Instruction

SQSHLU Hd,Hn,#n

Argument Preparation

a → Hn 
0 << n << 15

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQSHLU Sd,Sn,#n

Argument Preparation

a → Sn 
0 << n << 31

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQSHLU Dd,Dn,#n

Argument Preparation

a → Dn 
0 << n << 63

Result

Dd → result

Supported architectures

A64

A64 Instruction

SHRN Vd.8B,Vn.8H,#n

Argument Preparation

a → Vn.8H 
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SHRN Vd.4H,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SHRN Vd.2S,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SHRN Vd.8B,Vn.8H,#n

Argument Preparation

a → Vn.8H 
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SHRN Vd.4H,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SHRN Vd.2S,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SHRN2 Vd.16B,Vn.8H,#n

Argument Preparation

r → Vd.8B 
a → Vn.8H
1 << n << 8

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

SHRN2 Vd.8H,Vn.4S,#n

Argument Preparation

r → Vd.4H 
a → Vn.4S
1 << n << 16

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SHRN2 Vd.4S,Vn.2D,#n

Argument Preparation

r → Vd.2S 
a → Vn.2D
1 << n << 32

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SHRN2 Vd.16B,Vn.8H,#n

Argument Preparation

r → Vd.8B 
a → Vn.8H
1 << n << 8

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

SHRN2 Vd.8H,Vn.4S,#n

Argument Preparation

r → Vd.4H 
a → Vn.4S
1 << n << 16

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SHRN2 Vd.4S,Vn.2D,#n

Argument Preparation

r → Vd.2S 
a → Vn.2D
1 << n << 32

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQSHRUN Vd.8B,Vn.8H,#n

Argument Preparation

a → Vn.8H 
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHRUN Vd.4H,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHRUN Vd.2S,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHRUN Bd,Hn,#n

Argument Preparation

a → Hn 
1 << n << 8

Result

Bd → result

Supported architectures

A64

A64 Instruction

SQSHRUN Hd,Sn,#n

Argument Preparation

a → Sn 
1 << n << 16

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQSHRUN Sd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 32

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQSHRUN2 Vd.16B,Vn.8H,#n

Argument Preparation

r → Vd.8B 
a → Vn.8H
1 << n << 8

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

SQSHRUN2 Vd.8H,Vn.4S,#n

Argument Preparation

r → Vd.4H 
a → Vn.4S
1 << n << 16

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SQSHRUN2 Vd.4S,Vn.2D,#n

Argument Preparation

r → Vd.2S 
a → Vn.2D
1 << n << 32

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQRSHRUN Vd.8B,Vn.8H,#n

Argument Preparation

a → Vn.8H 
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRSHRUN Vd.4H,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRSHRUN Vd.2S,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRSHRUN Bd,Hn,#n

Argument Preparation

a → Hn 
1 << n << 8

Result

Bd → result

Supported architectures

A64

A64 Instruction

SQRSHRUN Hd,Sn,#n

Argument Preparation

a → Sn 
1 << n << 16

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQRSHRUN Sd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 32

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQRSHRUN2 Vd.16B,Vn.8H,#n

Argument Preparation

r → Vd.8B 
a → Vn.8H
1 << n << 8

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

SQRSHRUN2 Vd.8H,Vn.4S,#n

Argument Preparation

r → Vd.4H 
a → Vn.4S
1 << n << 16

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SQRSHRUN2 Vd.4S,Vn.2D,#n

Argument Preparation

r → Vd.2S 
a → Vn.2D
1 << n << 32

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQSHRN Vd.8B,Vn.8H,#n

Argument Preparation

a → Vn.8H 
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHRN Vd.4H,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHRN Vd.2S,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHRN Vd.8B,Vn.8H,#n

Argument Preparation

a → Vn.8H 
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHRN Vd.4H,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

UQSHRN Vd.2S,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQSHRN Bd,Hn,#n

Argument Preparation

a → Hn 
1 << n << 8

Result

Bd → result

Supported architectures

A64

A64 Instruction

SQSHRN Hd,Sn,#n

Argument Preparation

a → Sn 
1 << n << 16

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQSHRN Sd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 32

Result

Sd → result

Supported architectures

A64

A64 Instruction

UQSHRN Bd,Hn,#n

Argument Preparation

a → Hn 
1 << n << 8

Result

Bd → result

Supported architectures

A64

A64 Instruction

UQSHRN Hd,Sn,#n

Argument Preparation

a → Sn 
1 << n << 16

Result

Hd → result

Supported architectures

A64

A64 Instruction

UQSHRN Sd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 32

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQSHRN2 Vd.16B,Vn.8H,#n

Argument Preparation

r → Vd.8B 
a → Vn.8H
1 << n << 8

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

SQSHRN2 Vd.8H,Vn.4S,#n

Argument Preparation

r → Vd.4H 
a → Vn.4S
1 << n << 16

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SQSHRN2 Vd.4S,Vn.2D,#n

Argument Preparation

r → Vd.2S 
a → Vn.2D
1 << n << 32

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UQSHRN2 Vd.16B,Vn.8H,#n

Argument Preparation

r → Vd.8B 
a → Vn.8H
1 << n << 8

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

UQSHRN2 Vd.8H,Vn.4S,#n

Argument Preparation

r → Vd.4H 
a → Vn.4S
1 << n << 16

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

UQSHRN2 Vd.4S,Vn.2D,#n

Argument Preparation

r → Vd.2S 
a → Vn.2D
1 << n << 32

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

RSHRN Vd.8B,Vn.8H,#n

Argument Preparation

a → Vn.8H 
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

RSHRN Vd.4H,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

RSHRN Vd.2S,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

RSHRN Vd.8B,Vn.8H,#n

Argument Preparation

a → Vn.8H 
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

RSHRN Vd.4H,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

RSHRN Vd.2S,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

RSHRN2 Vd.16B,Vn.8H,#n

Argument Preparation

r → Vd.8B 
a → Vn.8H
1 << n << 8

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

RSHRN2 Vd.8H,Vn.4S,#n

Argument Preparation

r → Vd.4H 
a → Vn.4S
1 << n << 16

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

RSHRN2 Vd.4S,Vn.2D,#n

Argument Preparation

r → Vd.2S 
a → Vn.2D
1 << n << 32

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

RSHRN2 Vd.16B,Vn.8H,#n

Argument Preparation

r → Vd.8B 
a → Vn.8H
1 << n << 8

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

RSHRN2 Vd.8H,Vn.4S,#n

Argument Preparation

r → Vd.4H 
a → Vn.4S
1 << n << 16

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

RSHRN2 Vd.4S,Vn.2D,#n

Argument Preparation

r → 32(Vd) 
a → Vn.2D
1 << n << 32

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQRSHRN Vd.8B,Vn.8H,#n

Argument Preparation

a → Vn.8H 
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRSHRN Vd.4H,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRSHRN Vd.2S,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UQRSHRN Vd.8B,Vn.8H,#n

Argument Preparation

a → Vn.8H 
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

UQRSHRN Vd.4H,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

UQRSHRN Vd.2S,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRSHRN Bd,Hn,#n

Argument Preparation

a → Hn 
1 << n << 8

Result

Bd → result

Supported architectures

A64

A64 Instruction

SQRSHRN Hd,Sn,#n

Argument Preparation

a → Sn 
1 << n << 16

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQRSHRN Sd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 32

Result

Sd → result

Supported architectures

A64

A64 Instruction

UQRSHRN Bd,Hn,#n

Argument Preparation

a → Hn 
1 << n << 8

Result

Bd → result

Supported architectures

A64

A64 Instruction

UQRSHRN Hd,Sn,#n

Argument Preparation

a → Sn 
1 << n << 16

Result

Hd → result

Supported architectures

A64

A64 Instruction

UQRSHRN Sd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 32

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQRSHRN2 Vd.16B,Vn.8H,#n

Argument Preparation

r → Vd.8B 
a → Vn.8H
1 << n << 8

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

SQRSHRN2 Vd.8H,Vn.4S,#n

Argument Preparation

r → Vd.4H 
a → Vn.4S
1 << n << 16

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SQRSHRN2 Vd.4S,Vn.2D,#n

Argument Preparation

r → Vd.2S 
a → Vn.2D
1 << n << 32

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UQRSHRN2 Vd.16B,Vn.8H,#n

Argument Preparation

r → Vd.8B 
a → Vn.8H
1 << n << 8

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

UQRSHRN2 Vd.8H,Vn.4S,#n

Argument Preparation

r → Vd.4H 
a → Vn.4S
1 << n << 16

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

UQRSHRN2 Vd.4S,Vn.2D,#n

Argument Preparation

r → Vd.2S 
a → Vn.2D
1 << n << 32

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SSHLL Vd.8H,Vn.8B,#n

Argument Preparation

a → Vn.8B 
0 << n << 7

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHLL Vd.4S,Vn.4H,#n

Argument Preparation

a → Vn.4H 
0 << n << 15

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHLL Vd.2D,Vn.2S,#n

Argument Preparation

a → Vn.2S 
0 << n << 31

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

USHLL Vd.8H,Vn.8B,#n

Argument Preparation

a → Vn.8B 
0 << n << 7

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

USHLL Vd.4S,Vn.4H,#n

Argument Preparation

a → Vn.4H 
0 << n << 15

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

USHLL Vd.2D,Vn.2S,#n

Argument Preparation

a → Vn.2S 
0 << n << 31

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHLL2 Vd.8H,Vn.16B,#n

Argument Preparation

a → Vn.16B 
0 << n << 7

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SSHLL2 Vd.4S,Vn.8H,#n

Argument Preparation

a → Vn.8H 
0 << n << 15

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SSHLL2 Vd.2D,Vn.4S,#n

Argument Preparation

a → Vn.4S 
0 << n << 31

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

USHLL2 Vd.8H,Vn.16B,#n

Argument Preparation

a → Vn.16B 
0 << n << 7

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

USHLL2 Vd.4S,Vn.8H,#n

Argument Preparation

a → Vn.8H 
0 << n << 15

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

USHLL2 Vd.2D,Vn.4S,#n

Argument Preparation

a → Vn.4S 
0 << n << 31

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SHLL Vd.8H,Vn.8B,#n

Argument Preparation

a → Vn.8B 
8 << n << 8

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SHLL Vd.4S,Vn.4H,#n

Argument Preparation

a → Vn.4H 
16 << n << 16

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SHLL Vd.2D,Vn.2S,#n

Argument Preparation

a → Vn.2S 
32 << n << 32

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SHLL Vd.8H,Vn.8B,#n

Argument Preparation

a → Vn.8B 
8 << n << 8

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SHLL Vd.4S,Vn.4H,#n

Argument Preparation

a → Vn.4H 
16 << n << 16

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SHLL Vd.2D,Vn.2S,#n

Argument Preparation

a → Vn.2S 
32 << n << 32

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SHLL2 Vd.8H,Vn.16B,#n

Argument Preparation

a → Vn.16B 
8 << n << 8

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SHLL2 Vd.4S,Vn.8H,#n

Argument Preparation

a → Vn.8H 
16 << n << 16

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SHLL2 Vd.2D,Vn.4S,#n

Argument Preparation

a → Vn.4S 
32 << n << 32

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SHLL2 Vd.8H,Vn.16B,#n

Argument Preparation

a → Vn.16B 
8 << n << 8

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SHLL2 Vd.4S,Vn.8H,#n

Argument Preparation

a → Vn.8H 
16 << n << 16

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SHLL2 Vd.2D,Vn.4S,#n

Argument Preparation

a → Vn.4S 
32 << n << 32

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SRI Vd.8B,Vn.8B,#n

Argument Preparation

a → Vd.8B 
b → Vn.8B
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.16B,Vn.16B,#n

Argument Preparation

a → Vd.16B 
b → Vn.16B
1 << n << 8

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.4H,Vn.4H,#n

Argument Preparation

a → Vd.4H 
b → Vn.4H
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.8H,Vn.8H,#n

Argument Preparation

a → Vd.8H 
b → Vn.8H
1 << n << 16

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.2S,Vn.2S,#n

Argument Preparation

a → Vd.2S 
b → Vn.2S
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.4S,Vn.4S,#n

Argument Preparation

a → Vd.4S 
b → Vn.4S
1 << n << 32

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
1 << n << 64

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.2D,Vn.2D,#n

Argument Preparation

a → Vd.2D 
b → Vn.2D
1 << n << 64

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.8B,Vn.8B,#n

Argument Preparation

a → Vd.8B 
b → Vn.8B
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.16B,Vn.16B,#n

Argument Preparation

a → Vd.16B 
b → Vn.16B
1 << n << 8

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.4H,Vn.4H,#n

Argument Preparation

a → Vd.4H 
b → Vn.4H
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.8H,Vn.8H,#n

Argument Preparation

a → Vd.8H 
b → Vn.8H
1 << n << 16

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.2S,Vn.2S,#n

Argument Preparation

a → Vd.2S 
b → Vn.2S
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.4S,Vn.4S,#n

Argument Preparation

a → Vd.4S 
b → Vn.4S
1 << n << 32

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
1 << n << 64

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.2D,Vn.2D,#n

Argument Preparation

a → Vd.2D 
b → Vn.2D
1 << n << 64

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
1 << n << 64

Result

Dd → result

Supported architectures

A32/A64

A64 Instruction

SRI Vd.2D,Vn.2D,#n

Argument Preparation

a → Vd.2D 
b → Vn.2D
1 << n << 64

Result

Vd.2D → result

Supported architectures

A32/A64

A64 Instruction

SRI Vd.8B,Vn.8B,#n

Argument Preparation

a → Vd.8B 
b → Vn.8B
1 << n << 8

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.16B,Vn.16B,#n

Argument Preparation

a → Vd.16B 
b → Vn.16B
1 << n << 8

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.4H,Vn.4H,#n

Argument Preparation

a → Vd.4H 
b → Vn.4H
1 << n << 16

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Vd.8H,Vn.8H,#n

Argument Preparation

a → Vd.8H 
b → Vn.8H
1 << n << 16

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SRI Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

SRI Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

SLI Vd.8B,Vn.8B,#n

Argument Preparation

a → Vd.8B 
b → Vn.8B
0 << n << 7

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.16B,Vn.16B,#n

Argument Preparation

a → Vd.16B 
b → Vn.16B
0 << n << 7

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.4H,Vn.4H,#n

Argument Preparation

a → Vd.4H 
b → Vn.4H
0 << n << 15

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.8H,Vn.8H,#n

Argument Preparation

a → Vd.8H 
b → Vn.8H
0 << n << 15

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.2S,Vn.2S,#n

Argument Preparation

a → Vd.2S 
b → Vn.2S
0 << n << 31

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.4S,Vn.4S,#n

Argument Preparation

a → Vd.4S 
b → Vn.4S
0 << n << 31

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
0 << n << 63

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.2D,Vn.2D,#n

Argument Preparation

a → Vd.2D 
b → Vn.2D
0 << n << 63

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.8B,Vn.8B,#n

Argument Preparation

a → Vd.8B 
b → Vn.8B
0 << n << 7

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.16B,Vn.16B,#n

Argument Preparation

a → Vd.16B 
b → Vn.16B
0 << n << 7

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.4H,Vn.4H,#n

Argument Preparation

a → Vd.4H 
b → Vn.4H
0 << n << 15

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.8H,Vn.8H,#n

Argument Preparation

a → Vd.8H 
b → Vn.8H
0 << n << 15

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.2S,Vn.2S,#n

Argument Preparation

a → Vd.2S 
b → Vn.2S
0 << n << 31

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.4S,Vn.4S,#n

Argument Preparation

a → Vd.4S 
b → Vn.4S
0 << n << 31

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
0 << n << 63

Result

Dd → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.2D,Vn.2D,#n

Argument Preparation

a → Vd.2D 
b → Vn.2D
0 << n << 63

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
0 << n << 63

Result

Dd → result

Supported architectures

A32/A64

A64 Instruction

SLI Vd.2D,Vn.2D,#n

Argument Preparation

a → Vd.2D 
b → Vn.2D
0 << n << 63

Result

Vd.2D → result

Supported architectures

A32/A64

A64 Instruction

SLI Vd.8B,Vn.8B,#n

Argument Preparation

a → Vd.8B 
b → Vn.8B
0 << n << 7

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.16B,Vn.16B,#n

Argument Preparation

a → Vd.16B 
b → Vn.16B
0 << n << 7

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.4H,Vn.4H,#n

Argument Preparation

a → Vd.4H 
b → Vn.4H
0 << n << 15

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Vd.8H,Vn.8H,#n

Argument Preparation

a → Vd.8H 
b → Vn.8H
0 << n << 15

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SLI Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
0 << n << 63

Result

Dd → result

Supported architectures

A64

A64 Instruction

SLI Dd,Dn,#n

Argument Preparation

a → Dd 
b → Dn
0 << n << 63

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTZS Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCVTZS Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCVTZU Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCVTZU Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCVTNS Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FCVTNS Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FCVTNU Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FCVTNU Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FCVTMS Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FCVTMS Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FCVTMU Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FCVTMU Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FCVTPS Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FCVTPS Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FCVTPU Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FCVTPU Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FCVTAS Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FCVTAS Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FCVTAU Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FCVTAU Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FCVTZS Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCVTZU Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCVTNS Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCVTNU Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCVTMS Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCVTMU Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCVTPS Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCVTPU Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCVTAS Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCVTAU Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCVTZS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTZS Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCVTZU Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTZU Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCVTNS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTNS Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCVTNU Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTNU Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCVTMS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTMS Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCVTMU Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTMU Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCVTPS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTPS Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCVTPU Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTPU Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCVTAS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTAS Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCVTAU Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTAU Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCVTZS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTZU Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTNS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTNU Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTMS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTMU Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTPS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTPU Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTAS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTAU Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTZS Vd.2S,Vn.2S,#n

Argument Preparation

a → Vn.2S 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCVTZS Vd.4S,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 32

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCVTZU Vd.2S,Vn.2S,#n

Argument Preparation

a → Vn.2S 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCVTZU Vd.4S,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 32

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCVTZS Sd,Sn,#n

Argument Preparation

a → Sn 
1 << n << 32

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCVTZU Sd,Sn,#n

Argument Preparation

a → Sn 
1 << n << 32

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCVTZS Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTZS Vd.2D,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 64

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCVTZU Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTZU Vd.2D,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 64

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCVTZS Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTZU Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

SCVTF Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SCVTF Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UCVTF Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UCVTF Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SCVTF Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

UCVTF Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

SCVTF Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

SCVTF Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UCVTF Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

UCVTF Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SCVTF Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

UCVTF Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

SCVTF Vd.2S,Vn.2S,#n

Argument Preparation

a → Vn.2S 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SCVTF Vd.4S,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 32

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UCVTF Vd.2S,Vn.2S,#n

Argument Preparation

a → Vn.2S 
1 << n << 32

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UCVTF Vd.4S,Vn.4S,#n

Argument Preparation

a → Vn.4S 
1 << n << 32

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SCVTF Sd,Sn,#n

Argument Preparation

a → Sn 
1 << n << 32

Result

Sd → result

Supported architectures

A64

A64 Instruction

UCVTF Sd,Sn,#n

Argument Preparation

a → Sn 
1 << n << 32

Result

Sd → result

Supported architectures

A64

A64 Instruction

SCVTF Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

SCVTF Vd.2D,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 64

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UCVTF Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

UCVTF Vd.2D,Vn.2D,#n

Argument Preparation

a → Vn.2D 
1 << n << 64

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SCVTF Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

UCVTF Dd,Dn,#n

Argument Preparation

a → Dn 
1 << n << 64

Result

Dd → result

Supported architectures

A64

A64 Instruction

FCVTN Vd.4H,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

FCVTN2 Vd.8H,Vn.4S

Argument Preparation

r → Vd.4H 
a → Vn.4S

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

FCVTN Vd.2S,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FCVTN2 Vd.4S,Vn.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FCVTL Vd.4S,Vn.4H

Argument Preparation

a → Vn.4H 

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FCVTL2 Vd.4S,Vn.8H

Argument Preparation

a → Vn.8H 

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FCVTL Vd.2D,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCVTL2 Vd.2D,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FCVTXN Vd.2S,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FCVTXN Sd,Dn

Argument Preparation

a → Dn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

FCVTXN2 Vd.4S,Vn.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FRINTZ Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FRINTZ Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FRINTZ Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FRINTZ Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FRINTN Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FRINTN Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FRINTN Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A32/A64

A64 Instruction

FRINTN Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A32/A64

A64 Instruction

FRINTN Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A32/A64

A64 Instruction

FRINTM Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FRINTM Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FRINTM Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FRINTM Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FRINTP Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FRINTP Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FRINTP Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FRINTP Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FRINTA Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FRINTA Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FRINTA Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FRINTA Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FRINTI Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FRINTI Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FRINTI Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FRINTI Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FRINTX Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

A32/A64

A64 Instruction

FRINTX Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

A32/A64

A64 Instruction

FRINTX Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FRINTX Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

XTN Vd.8B,Vn.8H

Argument Preparation

a → Vn.8H 

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

XTN Vd.4H,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

XTN Vd.2S,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

XTN Vd.8B,Vn.8H

Argument Preparation

a → Vn.8H 

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

XTN Vd.4H,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

XTN Vd.2S,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

XTN2 Vd.16B,Vn.8H

Argument Preparation

r → Vd.8B 
a → Vn.8H

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

XTN2 Vd.8H,Vn.4S

Argument Preparation

r → Vd.4H 
a → Vn.4S

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

XTN2 Vd.4S,Vn.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

XTN2 Vd.16B,Vn.8H

Argument Preparation

r → Vd.8B 
a → Vn.8H

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

XTN2 Vd.8H,Vn.4S

Argument Preparation

r → Vd.4H 
a → Vn.4S

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

XTN2 Vd.4S,Vn.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SSHLL Vd.8H,Vn.8B,#0

Argument Preparation

a → Vn.8B 

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHLL Vd.4S,Vn.4H,#0

Argument Preparation

a → Vn.4H 

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHLL Vd.2D,Vn.2S,#0

Argument Preparation

a → Vn.2S 

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

USHLL Vd.8H,Vn.8B,#0

Argument Preparation

a → Vn.8B 

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

USHLL Vd.4S,Vn.4H,#0

Argument Preparation

a → Vn.4H 

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

USHLL Vd.2D,Vn.2S,#0

Argument Preparation

a → Vn.2S 

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SSHLL2 Vd.8H,Vn.16B,#0

Argument Preparation

a → Vn.16B 

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SSHLL2 Vd.4S,Vn.8H,#0

Argument Preparation

a → Vn.8H 

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SSHLL2 Vd.2D,Vn.4S,#0

Argument Preparation

a → Vn.4S 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

USHLL2 Vd.8H,Vn.16B,#0

Argument Preparation

a → Vn.16B 

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

USHLL2 Vd.4S,Vn.8H,#0

Argument Preparation

a → Vn.8H 

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

USHLL2 Vd.2D,Vn.4S,#0

Argument Preparation

a → Vn.4S 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQXTN Vd.8B,Vn.8H

Argument Preparation

a → Vn.8H 

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQXTN Vd.4H,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQXTN Vd.2S,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

UQXTN Vd.8B,Vn.8H

Argument Preparation

a → Vn.8H 

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

UQXTN Vd.4H,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

UQXTN Vd.2S,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQXTN Bd,Hn

Argument Preparation

a → Hn 

Result

Bd → result

Supported architectures

A64

A64 Instruction

SQXTN Hd,Sn

Argument Preparation

a → Sn 

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQXTN Sd,Dn

Argument Preparation

a → Dn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

UQXTN Bd,Hn

Argument Preparation

a → Hn 

Result

Bd → result

Supported architectures

A64

A64 Instruction

UQXTN Hd,Sn

Argument Preparation

a → Sn 

Result

Hd → result

Supported architectures

A64

A64 Instruction

UQXTN Sd,Dn

Argument Preparation

a → Dn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQXTN2 Vd.16B,Vn.8H

Argument Preparation

r → Vd.8B 
a → Vn.8H

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

SQXTN2 Vd.8H,Vn.4S

Argument Preparation

r → Vd.4H 
a → Vn.4S

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SQXTN2 Vd.4S,Vn.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UQXTN2 Vd.16B,Vn.8H

Argument Preparation

r → Vd.8B 
a → Vn.8H

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

UQXTN2 Vd.8H,Vn.4S

Argument Preparation

r → Vd.4H 
a → Vn.4S

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

UQXTN2 Vd.4S,Vn.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQXTUN Vd.8B,Vn.8H

Argument Preparation

a → Vn.8H 

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQXTUN Vd.4H,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQXTUN Vd.2S,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQXTUN Bd,Hn

Argument Preparation

a → Hn 

Result

Bd → result

Supported architectures

A64

A64 Instruction

SQXTUN Hd,Sn

Argument Preparation

a → Sn 

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQXTUN Sd,Dn

Argument Preparation

a → Dn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQXTUN2 Vd.16B,Vn.8H

Argument Preparation

r → Vd.8B 
a → Vn.8H

Result

Vd.16B → result

Supported architectures

A64

A64 Instruction

SQXTUN2 Vd.8H,Vn.4S

Argument Preparation

r → Vd.4H 
a → Vn.4S

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SQXTUN2 Vd.4S,Vn.2D

Argument Preparation

r → Vd.2S 
a → Vn.2D

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4H 
b → Vn.4H
v → Vm.4H
0 << lane << 3

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.8H 
b → Vn.8H
v → Vm.4H
0 << lane << 3

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2S 
b → Vn.2S
v → Vm.2S
0 << lane << 1

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4S
v → Vm.2S
0 << lane << 1

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4H 
b → Vn.4H
v → Vm.4H
0 << lane << 3

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.8H 
b → Vn.8H
v → Vm.4H
0 << lane << 3

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2S 
b → Vn.2S
v → Vm.2S
0 << lane << 1

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4S
v → Vm.2S
0 << lane << 1

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

IGNORE

Argument Preparation

0 << lane << 1 

Result

N/A → result

Supported architectures

v7/A32/A64

A64 Instruction

IGNORE

Argument Preparation

0 << lane << 1 

Result

N/A → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4H 
b → Vn.4H
v → Vm.8H
0 << lane << 7

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.8H 
b → Vn.8H
v → Vm.8H
0 << lane << 7

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2S 
b → Vn.2S
v → Vm.4S
0 << lane << 3

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4S
v → Vm.4S
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4H 
b → Vn.4H
v → Vm.8H
0 << lane << 7

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.8H 
b → Vn.8H
v → Vm.8H
0 << lane << 7

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2S 
b → Vn.2S
v → Vm.4S
0 << lane << 3

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4S
v → Vm.4S
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

IGNORE

Argument Preparation

0 << lane << 3 

Result

N/A → result

Supported architectures

A64

A64 Instruction

IGNORE

Argument Preparation

0 << lane << 3 

Result

N/A → result

Supported architectures

A64

A64 Instruction

SMLAL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4H
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLAL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2S
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UMLAL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4H
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UMLAL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2S
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLAL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.8H
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMLAL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.4S
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMLAL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.8H
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMLAL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.4S
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SMLAL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4H
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMLAL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2S
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMLAL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4H
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMLAL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2S
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SMLAL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.8H
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMLAL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.4S
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMLAL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.8H
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMLAL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.4S
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQDMLAL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4H
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMLAL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2S
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMLAL Sd,Hn,Vm.H[lane]

Argument Preparation

a → Sd 
b → Hn
v → Vm.4H
0 << lane << 3

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQDMLAL Dd,Sn,Vm.S[lane]

Argument Preparation

a → Dd 
b → Sn
v → Vm.2S
0 << lane << 1

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.8H
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.4S
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQDMLAL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4H
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMLAL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2S
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQDMLAL Sd,Hn,Vm.H[lane]

Argument Preparation

a → Sd 
b → Hn
v → Vm.8H
0 << lane << 7

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQDMLAL Dd,Sn,Vm.S[lane]

Argument Preparation

a → Dd 
b → Sn
v → Vm.4S
0 << lane << 3

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.8H
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.4S
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4H 
b → Vn.4H
v → Vm.4H
0 << lane << 3

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.8H 
b → Vn.8H
v → Vm.4H
0 << lane << 3

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2S 
b → Vn.2S
v → Vm.2S
0 << lane << 1

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4S
v → Vm.2S
0 << lane << 1

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4H 
b → Vn.4H
v → Vm.4H
0 << lane << 3

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.8H 
b → Vn.8H
v → Vm.4H
0 << lane << 3

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2S 
b → Vn.2S
v → Vm.2S
0 << lane << 1

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4S
v → Vm.2S
0 << lane << 1

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

IGNORE

Argument Preparation

0 << lane << 1 

Result

N/A → result

Supported architectures

v7/A32/A64

A64 Instruction

IGNORE

Argument Preparation

0 << lane << 1 

Result

N/A → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4H 
b → Vn.4H
v → Vm.8H
0 << lane << 7

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.8H 
b → Vn.8H
v → Vm.8H
0 << lane << 7

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2S 
b → Vn.2S
v → Vm.4S
0 << lane << 3

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4S
v → Vm.4S
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4H 
b → Vn.4H
v → Vm.8H
0 << lane << 7

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.8H 
b → Vn.8H
v → Vm.8H
0 << lane << 7

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2S 
b → Vn.2S
v → Vm.4S
0 << lane << 3

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4S
v → Vm.4S
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

IGNORE

Argument Preparation

0 << lane << 3 

Result

N/A → result

Supported architectures

A64

A64 Instruction

IGNORE

Argument Preparation

0 << lane << 3 

Result

N/A → result

Supported architectures

A64

A64 Instruction

SMLSL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4H
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLSL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2S
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UMLSL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4H
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UMLSL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2S
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLSL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.8H
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMLSL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.4S
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMLSL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.8H
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMLSL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.4S
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SMLSL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4H
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMLSL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2S
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMLSL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4H
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMLSL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2S
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SMLSL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.8H
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMLSL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.4S
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMLSL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.8H
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMLSL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.4S
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQDMLSL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4H
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMLSL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2S
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMLSL Sd,Hn,Vm.H[lane]

Argument Preparation

a → Sd 
b → Hn
v → Vm.4H
0 << lane << 3

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQDMLSL Dd,Sn,Vm.S[lane]

Argument Preparation

a → Dd 
b → Sn
v → Vm.2S
0 << lane << 1

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.8H
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.4S
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQDMLSL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.4H
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMLSL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.2S
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQDMLSL Sd,Hn,Vm.H[lane]

Argument Preparation

a → Sd 
b → Hn
v → Vm.8H
0 << lane << 7

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQDMLSL Dd,Sn,Vm.S[lane]

Argument Preparation

a → Dd 
b → Sn
v → Vm.4S
0 << lane << 3

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vd.4S 
b → Vn.8H
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vd.2D 
b → Vn.4S
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[0]

Argument Preparation

a → Vn.4H 
b → Vm.H[0]

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[0]

Argument Preparation

a → Vn.8H 
b → Vm.H[0]

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[0]

Argument Preparation

a → Vn.2S 
b → Vm.S[0]

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[0]

Argument Preparation

a → Vn.4S 
b → Vm.S[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[0]

Argument Preparation

a → Vn.4H 
b → Vm.H[0]

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[0]

Argument Preparation

a → Vn.8H 
b → Vm.H[0]

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[0]

Argument Preparation

a → Vn.2S 
b → Vm.S[0]

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[0]

Argument Preparation

a → Vn.4S 
b → Vm.S[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMUL Vd.2S,Vn.2S,Vm.S[0]

Argument Preparation

a → Vn.2S 
b → Vm.S[0]

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMUL Vd.4S,Vn.4S,Vm.S[0]

Argument Preparation

a → Vn.4S 
b → Vm.S[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMUL Dd,Dn,Vm.D[0]

Argument Preparation

a → Dn 
b → Vm.D[0]

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMUL Vd.2D,Vn.2D,Vm.D[0]

Argument Preparation

a → Vn.2D 
b → Vm.D[0]

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vn.4H 
v → Vm.4H
0 << lane << 3

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vn.8H 
v → Vm.4H
0 << lane << 3

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.2S
0 << lane << 1

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.2S
0 << lane << 1

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vn.4H 
v → Vm.4H
0 << lane << 3

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vn.8H 
v → Vm.4H
0 << lane << 3

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.2S
0 << lane << 1

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.2S
0 << lane << 1

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMUL Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.2S
0 << lane << 1

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMUL Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.2S
0 << lane << 1

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FMUL Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dn 
v → Vm.1D
0 << lane << 0

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMUL Vd.2D,Vn.2D,Vm.D[lane]

Argument Preparation

a → Vn.2D 
v → Vm.1D
0 << lane << 0

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMUL Sd,Sn,Vm.S[lane]

Argument Preparation

a → Sn 
v → Vm.2S
0 << lane << 1

Result

Sd → result

Supported architectures

A64

A64 Instruction

FMUL Dd,Dn,Vm.S[lane]

Argument Preparation

a → Dn 
v → Vm.1D
0 << lane << 0

Result

Dd → result

Supported architectures

A64

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vn.4H 
v → Vm.8H
0 << lane << 7

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vn.8H 
v → Vm.8H
0 << lane << 7

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.4S
0 << lane << 3

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.4S
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vn.4H 
v → Vm.8H
0 << lane << 7

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vn.8H 
v → Vm.8H
0 << lane << 7

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.4S
0 << lane << 3

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.4S
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FMUL Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.4S
0 << lane << 3

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

FMUL Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.4S
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

FMUL Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dn 
v → Vm.2D
0 << lane << 1

Result

Dd → result

Supported architectures

A64

A64 Instruction

FMUL Vd.2D,Vn.2D,Vm.D[lane]

Argument Preparation

a → Vn.2D 
v → Vm.2D
0 << lane << 1

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FMUL Sd,Sn,Vm.S[lane]

Argument Preparation

a → Sn 
v → Vm.4S
0 << lane << 3

Result

Sd → result

Supported architectures

A64

A64 Instruction

FMUL Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dn 
v → Vm.2D
0 << lane << 1

Result

Dd → result

Supported architectures

A64

A64 Instruction

SMULL Vd.4S,Vn.4H,Vm.H[0]

Argument Preparation

a → Vn.4H 
b → Vm.H[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SMULL Vd.2D,Vn.2S,Vm.S[0]

Argument Preparation

a → Vn.2S 
b → Vm.S[0]

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UMULL Vd.4S,Vn.4H,Vm.H[0]

Argument Preparation

a → Vn.4H 
b → Vm.H[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UMULL Vd.2D,Vn.2S,Vm.S[0]

Argument Preparation

a → Vn.2S 
b → Vm.S[0]

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SMULL2 Vd.4S,Vn.8H,Vm.H[0]

Argument Preparation

a → Vn.8H 
b → Vm.H[0]

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMULL2 Vd.2D,Vn.4S,Vm.S[0]

Argument Preparation

a → Vn.4S 
b → Vm.S[0]

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMULL2 Vd.4S,Vn.8H,Vm.H[0]

Argument Preparation

a → Vn.8H 
b → Vm.H[0]

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMULL2 Vd.2D,Vn.4S,Vm.S[0]

Argument Preparation

a → Vn.4S 
b → Vm.S[0]

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SMULL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vn.4H 
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SMULL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UMULL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vn.4H 
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UMULL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SMULL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vn.8H 
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMULL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMULL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vn.8H 
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMULL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SMULL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vn.4H 
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMULL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMULL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vn.4H 
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMULL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SMULL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vn.8H 
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMULL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMULL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vn.8H 
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMULL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQDMULL Vd.4S,Vn.4H,Vm.H[0]

Argument Preparation

a → Vn.4H 
b → Vm.H[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULL Vd.2D,Vn.2S,Vm.S[0]

Argument Preparation

a → Vn.2S 
b → Vm.S[0]

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULL2 Vd.4S,Vn.8H,Vm.H[0]

Argument Preparation

a → Vn.8H 
b → Vm.H[0]

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMULL2 Vd.2D,Vn.4S,Vm.S[0]

Argument Preparation

a → Vn.4S 
b → Vm.S[0]

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQDMULL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vn.4H 
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULL Sd,Hn,Vm.H[lane]

Argument Preparation

a → Hn 
v → Vm.4H
0 << lane << 3

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQDMULL Dd,Sn,Vm.S[lane]

Argument Preparation

a → Sn 
v → Vm.2S
0 << lane << 1

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vn.8H 
v → Vm.4H
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.2S
0 << lane << 1

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQDMULL Vd.4S,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vn.4H 
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMULL Vd.2D,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQDMULL Sd,Hn,Vm.H[lane]

Argument Preparation

a → Hn 
v → Vm.8H
0 << lane << 7

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQDMULL Dd,Sn,Vm.S[lane]

Argument Preparation

a → Sn 
v → Vm.4S
0 << lane << 3

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vn.8H 
v → Vm.8H
0 << lane << 7

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.4S
0 << lane << 3

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQDMULH Vd.4H,Vn.4H,Vm.H[0]

Argument Preparation

a → Vn.4H 
b → Vm.H[0]

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULH Vd.8H,Vn.8H,Vm.H[0]

Argument Preparation

a → Vn.8H 
b → Vm.H[0]

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULH Vd.2S,Vn.2S,Vm.S[0]

Argument Preparation

a → Vn.2S 
b → Vm.S[0]

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULH Vd.4S,Vn.4S,Vm.S[0]

Argument Preparation

a → Vn.4S 
b → Vm.S[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULH Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vn.4H 
v → Vm.4H
0 << lane << 3

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULH Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vn.8H 
v → Vm.4H
0 << lane << 3

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULH Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.2S
0 << lane << 1

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULH Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.2S
0 << lane << 1

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMULH Hd,Hn,Vm.H[lane]

Argument Preparation

a → Hn 
v → Vm.4H
0 << lane << 3

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQDMULH Sd,Sn,Vm.H[lane]

Argument Preparation

a → Sn 
v → Vm.2S
0 << lane << 1

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQDMULH Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vn.4H 
v → Vm.8H
0 << lane << 7

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

SQDMULH Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vn.8H 
v → Vm.8H
0 << lane << 7

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SQDMULH Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.4S
0 << lane << 3

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

SQDMULH Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.4S
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMULH Hd,Hn,Vm.H[lane]

Argument Preparation

a → Hn 
v → Vm.8H
0 << lane << 7

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQDMULH Sd,Sn,Vm.H[lane]

Argument Preparation

a → Sn 
v → Vm.4S
0 << lane << 3

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQRDMULH Vd.4H,Vn.4H,Vm.H[0]

Argument Preparation

a → Vn.4H 
b → Vm.H[0]

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRDMULH Vd.8H,Vn.8H,Vm.H[0]

Argument Preparation

a → Vn.8H 
b → Vm.H[0]

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRDMULH Vd.2S,Vn.2S,Vm.S[0]

Argument Preparation

a → Vn.2S 
b → Vm.S[0]

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRDMULH Vd.4S,Vn.4S,Vm.S[0]

Argument Preparation

a → Vn.4S 
b → Vm.S[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRDMULH Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vn.4H 
v → Vm.4H
0 << lane << 3

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRDMULH Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vn.8H 
v → Vm.4H
0 << lane << 3

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRDMULH Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.2S
0 << lane << 1

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRDMULH Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.2S
0 << lane << 1

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQRDMULH Hd,Hn,Vm.H[lane]

Argument Preparation

a → Hn 
v → Vm.4H
0 << lane << 3

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQRDMULH Sd,Sn,Vm.S[lane]

Argument Preparation

a → Sn 
v → Vm.2S
0 << lane << 1

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQRDMULH Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation

a → Vn.4H 
v → Vm.8H
0 << lane << 7

Result

Vd.4H → result

Supported architectures

A64

A64 Instruction

SQRDMULH Vd.8H,Vn.8H,Vm.H[lane]

Argument Preparation

a → Vn.8H 
v → Vm.8H
0 << lane << 7

Result

Vd.8H → result

Supported architectures

A64

A64 Instruction

SQRDMULH Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 
v → Vm.4S
0 << lane << 3

Result

Vd.2S → result

Supported architectures

A64

A64 Instruction

SQRDMULH Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 
v → Vm.4S
0 << lane << 3

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQRDMULH Hd,Hn,Vm.H[lane]

Argument Preparation

a → Hn 
v → Vm.8H
0 << lane << 7

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQRDMULH Sd,Sn,Vm.S[lane]

Argument Preparation

a → Sn 
v → Vm.4S
0 << lane << 3

Result

Sd → result

Supported architectures

A64

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[0]

Argument Preparation

a → Vd.4H 
b → Vn.4H
c → Vm.H[0]

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[0]

Argument Preparation

a → Vd.8H 
b → Vn.8H
c → Vm.H[0]

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[0]

Argument Preparation

a → Vd.2S 
b → Vn.2S
c → Vm.S[0]

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[0]

Argument Preparation

a → Vd.4S 
b → Vn.4S
c → Vm.S[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[0]

Argument Preparation

a → Vd.4H 
b → Vn.4H
c → Vm.H[0]

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[0]

Argument Preparation

a → Vd.8H 
b → Vn.8H
c → Vm.H[0]

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[0]

Argument Preparation

a → Vd.2S 
b → Vn.2S
c → Vm.S[0]

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[0]

Argument Preparation

a → Vd.4S 
b → Vn.4S
c → Vm.S[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

IGNORE

Argument Preparation

a → N/A 
b → N/A
c → N/A

Result

N/A → result

Supported architectures

v7/A32/A64

A64 Instruction

IGNORE

Argument Preparation

a → N/A 
b → N/A
c → N/A

Result

N/A → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLAL Vd.4S,Vn.4H,Vm.H[0]

Argument Preparation

a → Vd.4S 
b → Vn.4H
c → Vm.H[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLAL Vd.2D,Vn.2S,Vm.S[0]

Argument Preparation

a → Vd.2D 
b → Vn.2S
c → Vm.S[0]

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UMLAL Vd.4S,Vn.4H,Vm.H[0]

Argument Preparation

a → Vd.4S 
b → Vn.4H
c → Vm.H[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UMLAL Vd.2D,Vn.2S,Vm.S[0]

Argument Preparation

a → Vd.2D 
b → Vn.2S
c → Vm.S[0]

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLAL2 Vd.4S,Vn.8H,Vm.H[0]

Argument Preparation

a → Vd.4S 
b → Vn.8H
c → Vm.H[0]

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMLAL2 Vd.2D,Vn.4S,Vm.S[0]

Argument Preparation

a → Vd.2D 
b → Vn.4S
c → Vm.S[0]

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMLAL2 Vd.4S,Vn.8H,Vm.H[0]

Argument Preparation

a → Vd.4S 
b → Vn.8H
c → Vm.H[0]

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMLAL2 Vd.2D,Vn.4S,Vm.S[0]

Argument Preparation

a → Vd.2D 
b → Vn.4S
c → Vm.S[0]

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQDMLAL Vd.4S,Vn.4H,Vm.H[0]

Argument Preparation

a → Vd.4S 
b → Vn.4H
c → Vm.H[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMLAL Vd.2D,Vn.2S,Vm.S[0]

Argument Preparation

a → Vd.2D 
b → Vn.2S
c → Vm.S[0]

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMLAL2 Vd.4S,Vn.8H,Vm.H[0]

Argument Preparation

a → Vd.4S 
b → Vn.8H
c → Vm.H[0]

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMLAL2 Vd.2D,Vn.4S,Vm.S[0]

Argument Preparation

a → Vd.2D 
b → Vn.4S
c → Vm.S[0]

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[0]

Argument Preparation

a → Vd.4H 
b → Vn.4H
c → Vm.H[0]

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[0]

Argument Preparation

a → Vd.8H 
b → Vn.8H
c → Vm.H[0]

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[0]

Argument Preparation

a → Vd.2S 
b → Vn.2S
c → Vm.S[0]

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[0]

Argument Preparation

a → Vd.4S 
b → Vn.4S
c → Vm.S[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[0]

Argument Preparation

a → Vd.4H 
b → Vn.4H
c → Vm.H[0]

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[0]

Argument Preparation

a → Vd.8H 
b → Vn.8H
c → Vm.H[0]

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[0]

Argument Preparation

a → Vd.2S 
b → Vn.2S
c → Vm.S[0]

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[0]

Argument Preparation

a → Vd.4S 
b → Vn.4S
c → Vm.S[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

IGNORE

Argument Preparation

a → N/A 
b → N/A
c → N/A

Result

N/A → result

Supported architectures

v7/A32/A64

A64 Instruction

IGNORE

Argument Preparation

a → N/A 
b → N/A
c → N/A

Result

N/A → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLSL Vd.4S,Vn.4H,Vm.H[0]

Argument Preparation

a → Vd.4S 
b → Vn.4H
c → Vm.H[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLSL Vd.2D,Vn.2S,Vm.S[0]

Argument Preparation

a → Vd.2D 
b → Vn.2S
c → Vm.S[0]

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

UMLSL Vd.4S,Vn.4H,Vm.H[0]

Argument Preparation

a → Vd.4S 
b → Vn.4H
c → Vm.H[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

UMLSL Vd.2D,Vn.2S,Vm.S[0]

Argument Preparation

a → Vd.2D 
b → Vn.2S
c → Vm.S[0]

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SMLSL2 Vd.4S,Vn.8H,Vm.H[0]

Argument Preparation

a → Vd.4S 
b → Vn.8H
c → Vm.H[0]

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SMLSL2 Vd.2D,Vn.4S,Vm.S[0]

Argument Preparation

a → Vd.2D 
b → Vn.4S
c → Vm.S[0]

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

UMLSL2 Vd.4S,Vn.8H,Vm.H[0]

Argument Preparation

a → Vd.4S 
b → Vn.8H
c → Vm.H[0]

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

UMLSL2 Vd.2D,Vn.4S,Vm.S[0]

Argument Preparation

a → Vd.2D 
b → Vn.4S
c → Vm.S[0]

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQDMLSL Vd.4S,Vn.4H,Vm.H[0]

Argument Preparation

a → Vd.4S 
b → Vn.4H
c → Vm.H[0]

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMLSL Vd.2D,Vn.2S,Vm.S[0]

Argument Preparation

a → Vd.2D 
b → Vn.2S
c → Vm.S[0]

Result

Vd.2D → result

Supported architectures

v7/A32/A64

A64 Instruction

SQDMLSL2 Vd.4S,Vn.8H,Vm.H[0]

Argument Preparation

a → Vd.4S 
b → Vn.8H
c → Vm.H[0]

Result

Vd.4S → result

Supported architectures

A64

A64 Instruction

SQDMLSL2 Vd.2D,Vn.4S,Vm.S[0]

Argument Preparation

a → Vd.2D 
b → Vn.4S
c → Vm.S[0]

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

ABS Vd.8B,Vn.8B

Argument Preparation

a → Vn.8B 

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

ABS Vd.16B,Vn.16B

Argument Preparation

a → Vn.16B 

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

ABS Vd.4H,Vn.4H

Argument Preparation

a → Vn.4H 

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

ABS Vd.8H,Vn.8H

Argument Preparation

a → Vn.8H 

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

ABS Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

ABS Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FABS Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FABS Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

ABS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

ABS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

ABS Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FABS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FABS Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQABS Vd.8B,Vn.8B

Argument Preparation

a → Vn.8B 

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQABS Vd.16B,Vn.16B

Argument Preparation

a → Vn.16B 

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQABS Vd.4H,Vn.4H

Argument Preparation

a → Vn.4H 

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQABS Vd.8H,Vn.8H

Argument Preparation

a → Vn.8H 

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQABS Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQABS Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQABS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQABS Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQABS Bd,Bn

Argument Preparation

a → Bn 

Result

Bd → result

Supported architectures

A64

A64 Instruction

SQABS Hd,Hn

Argument Preparation

a → Hn 

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQABS Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQABS Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

NEG Vd.8B,Vn.8B

Argument Preparation

a → Vn.8B 

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

NEG Vd.16B,Vn.16B

Argument Preparation

a → Vn.16B 

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

NEG Vd.4H,Vn.4H

Argument Preparation

a → Vn.4H 

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

NEG Vd.8H,Vn.8H

Argument Preparation

a → Vn.8H 

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

NEG Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

NEG Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

FNEG Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

FNEG Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

NEG Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

NEG Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

NEG Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

FNEG Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

FNEG Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQNEG Vd.8B,Vn.8B

Argument Preparation

a → Vn.8B 

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQNEG Vd.16B,Vn.16B

Argument Preparation

a → Vn.16B 

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

SQNEG Vd.4H,Vn.4H

Argument Preparation

a → Vn.4H 

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQNEG Vd.8H,Vn.8H

Argument Preparation

a → Vn.8H 

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

SQNEG Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQNEG Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

SQNEG Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

SQNEG Vd.2D,Vn.2D

Argument Preparation

a → Vn.2D 

Result

Vd.2D → result

Supported architectures

A64

A64 Instruction

SQNEG Bd,Bn

Argument Preparation

a → Bn 

Result

Bd → result

Supported architectures

A64

A64 Instruction

SQNEG Hd,Hn

Argument Preparation

a → Hn 

Result

Hd → result

Supported architectures

A64

A64 Instruction

SQNEG Sd,Sn

Argument Preparation

a → Sn 

Result

Sd → result

Supported architectures

A64

A64 Instruction

SQNEG Dd,Dn

Argument Preparation

a → Dn 

Result

Dd → result

Supported architectures

A64

A64 Instruction

CLS Vd.8B,Vn.8B

Argument Preparation

a → Vn.8B 

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CLS Vd.16B,Vn.16B

Argument Preparation

a → Vn.16B 

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CLS Vd.4H,Vn.4H

Argument Preparation

a → Vn.4H 

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

CLS Vd.8H,Vn.8H

Argument Preparation

a → Vn.8H 

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

CLS Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A64 Instruction

CLS Vd.4S,Vn.4S

Argument Preparation

a → Vn.4S 

Result

Vd.4S → result

Supported architectures

v7/A32/A64

A64 Instruction

CLZ Vd.8B,Vn.8B

Argument Preparation

a → Vn.8B 

Result

Vd.8B → result

Supported architectures

v7/A32/A64

A64 Instruction

CLZ Vd.16B,Vn.16B

Argument Preparation

a → Vn.16B 

Result

Vd.16B → result

Supported architectures

v7/A32/A64

A64 Instruction

CLZ Vd.4H,Vn.4H

Argument Preparation

a → Vn.4H 

Result

Vd.4H → result

Supported architectures

v7/A32/A64

A64 Instruction

CLZ Vd.8H,Vn.8H

Argument Preparation

a → Vn.8H 

Result

Vd.8H → result

Supported architectures

v7/A32/A64

A64 Instruction

CLZ Vd.2S,Vn.2S

Argument Preparation

a → Vn.2S 

Result

Vd.2S → result

Supported architectures

v7/A32/A64

A6