Hardware architecture: enabling a ‘secure’ and a ‘non-secure’ world
The goal of the Arm TrustZone hardware architecture
The primary security objective of the Arm TrustZone hardware architecture is actually rather simple - to enable the construction of a programmable environment that allows the confidentiality and integrity of almost any asset to be protected from specific attacks. A platform with these characteristics can be used to build a wide-ranging set of security solutions which are not cost-effective with traditional methods.
Instead of providing a fixed one-size-fits-all security solution, Arm TrustZone technology provides the infrastructure foundations, that allow the SoC designer to choose from a range of components that can fulfil specific functions within the security environment.
The security of the system is achieved by partitioning all of the SoC's hardware and software resources so that they exist in one of two worlds - the secure world for the security subsystem and the non-secure world for everything else.
How it works: Arm TrustZone-enabled AMBA bus fabric
Hardware logic present in the Arm TrustZone-enabled AMBA bus fabric ensures that no secure world resources can be accessed by the non-secure world components, enabling a strong security perimeter to be built between the two. A design that places sensitive resources in the secure world, and implements robust software running on the secure processor cores, can protect almost any asset against many of the possible attacks. This includes those which are normally difficult to secure, such as passwords entered using a keyboard or touch-screen.
How it works: using processor extensions
Another key advantage of the Arm TrustZone hardware architecture is the extensions that have been implemented in some of the Arm processor cores. These additions enable a single physical processor core to safely and efficiently execute code from both the ‘normal world’ and the ‘secure world’ in a time-sliced fashion. This removes the need for a dedicated security processor core, which saves silicon area and power. It also allows high performance security software to run alongside the ‘normal world’ operating environment. Each physical processor core provides two virtual cores, one considered ‘non-secure’ and the other ‘secure’, plus a mechanism to robustly context switch between them. The security state is encoded on the system bus and this enables trivial integration of the virtual processors into the system security mechanism; the ‘non-secure’ virtual processor can only access ‘non-secure’ system resources, but the ‘secure’ virtual processor can see all resources.
How it works: security-aware debug infrastructure
The final aspect of the Arm TrustZone hardware architecture is a security-aware debug infrastructure, which can enable control over access to secure world debug, without impairing debug visibility of the ‘normal’ world. For Arm Cortex-A processors that support the security extensions, the transition between ‘non-secure’ world and ‘secure’ world is managed by software via a Secure Monitor Call (SMC) which runs at the highest level of privilege e.g. Exception Level 3 (EL3). For microcontrollers that support Arm TrustZone, the world switch is a hardware transition which is more appropriate for resource constrained chips.