Arm development boards are the ideal platform for accelerating the development and reducing the risk of new SoC designs. The combination of ASIC and FPGA technology in Arm boards delivers an optimal solution in terms of speed, accuracy, flexibility and cost.
Key Benefits:
- Evaluate, benchmark and start software development using the latest Arm processors.
- Prototype, validate and develop software drivers for new SoC IP blocks.
- Test custom logic blocks or system IP in an FPGA, connected to an Arm core running at ASIC speed.
IoT Test Chip Boards
Arm creates a range of boards to enable easier development or evaluation of Arm IP in real-life conditions. The Arm IoT test chips are based on subsystem IP, offering a foundation for your future designs.
Juno Development Platform
The Armv8-A development platform, also known as Juno, is a software development platform that includes the Juno Arm Versatile Express board and an Armv8-A reference software port available through Linaro.
Neoverse N1 SDP
Neoverse N1 SDP is an infrastructure segment development platform available for licensing to Arm partners. The platform supports a reference open-source software stack based on Trusted Firmware-A, SCP-firmware, EDK II UEFI, GRUB, Linux, and user-space components.
FPGA Prototyping Boards
Arm provides a selection of boards available for prototyping, evaluation and benchmarking on Arm Cortex-based designs or IoT subsystems in FPGA.
DesignStart DAPLink Board
The Arm DesignStart DAPLink board can be used to provide DAPLink debug access to the Arm DesignStart Cortex-M1, Cortex-M3 Xilinx Digilent Arty-A7, and Digilent Arty-S7 FPGA evaluation platforms.
Choosing a Board
Find the most appropriate board for your project.
| IP | Juno development platform | Motherboard Express and LogicTile Express FPGA prototyping boards (Soft Macro Model) | MPS2+ FPGA prototyping board | MPS3 FPGA prototyping board | Musca IoT board | Beetle IoT board | Keil evaluation boards | Mbed development boards |
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| Cortex-M23 | |
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| Cortex-M4 | |
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| Cortex-M1 | |
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| Cortex-M0 | |
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| Cortex-M3 DesignStart / CoreLink SSE-050 Subsystem (based on Cortex-M3) |
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| CoreLink SSE-200 Subsystem (based on Cortex-M33) |
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| SSE-123 Example Subsystem | |
Community Forums
| Answered | GCC linker error | 0 votes | 351 views | 3 replies | Latest 29 days ago by Andy Neil | Answer this |
| Answered | How to make Ethos-U NPU work on an ARM Cortex-A + Cortex-M processor? | 0 votes | 10975 views | 38 replies | Latest 1 months ago by Kristofer Jonsson | Answer this |
| Answered | Specific migration related questions from 5.06 to 6.15 | 0 votes | 613 views | 9 replies | Latest 1 months ago by Alam | Answer this |
| Answered | about determining cold boot, warm boot | 0 votes | 2072 views | 5 replies | Latest 1 months ago by Zhifei Yang | Answer this |
| Answered | how to build u-boot for AEMv8A FVP? | 0 votes | 463 views | 1 replies | Latest 1 months ago by Stanilsav | Answer this |
| Answered | What program is giving the debug info, is it gcc or gdb? | 0 votes | 847 views | 3 replies | Latest 1 months ago by Andy Neil | Answer this |
| Answered | GCC linker error Latest 29 days ago by Andy Neil | 3 replies 351 views |
| Answered | How to make Ethos-U NPU work on an ARM Cortex-A + Cortex-M processor? Latest 1 months ago by Kristofer Jonsson | 38 replies 10975 views |
| Answered | Specific migration related questions from 5.06 to 6.15 Latest 1 months ago by Alam | 9 replies 613 views |
| Answered | about determining cold boot, warm boot Latest 1 months ago by Zhifei Yang | 5 replies 2072 views |
| Answered | how to build u-boot for AEMv8A FVP? Latest 1 months ago by Stanilsav | 1 replies 463 views |
| Answered | What program is giving the debug info, is it gcc or gdb? Latest 1 months ago by Andy Neil | 3 replies 847 views |