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5.5.3. Application note .txt file

Example 5.12 shows the contents of a typical application note axxxrnpm.txt file.

BOARD: HBI0192
TITLE: AN224

[FPGAS]
TOTALFPGAS: 1                   ;Total Number of FPGAS (Max:8)
F0FILE: a224r0p0.bit            ;FPGA0 Filename
F0MODE: FPGA                    ;FPGA0 Programming Mode

[OSCCLKS]
TOTALOSCCLKS: 6                 ;Total Number of OSCCLKS (Max:8)
OSC0: 90.0                      ;OSC0 Frequency in MHz (ACLK)
OSC1: 23.75                     ;OSC1 Frequency in MHz (CLCD)
OSC2: 133.0                     ;OSC2 Frequency in MHz (ZBTRAM)
OSC3: 33.0                      ;OSC3 Frequency in MHz (ExtS ACLK)
OSC4: 50.0                      ;OSC4 Frequency in MHz (SMB)
OSC5: 50.0                      ;OSC5 Frequency in MHz (Not used)

[SCC REGISTERS]
TOTALSCCS: 2                    ;Total Number of SCC registers defined
SCC: 0x000 0x01234567           ;SCC general read/write register address/value
SCC: 0x004 0x89ABCDEF           ;SCC general read/write register address/value

FPGAS section

The FPGAS section lists the FPGAs on the daughterboard, the images to load and the FPGA programming mode.

FxMODE selects the programming mode.

  • FPGA_STREAM:

    • This is a debug mode that programs the FPGA directly from the microSD card without using NAND memory.

  • FPGA:

    • This mode uses the daughterboard NAND memory to configure the FPGA. If the LogicTile contains more than one FPGA, this mode configureS the FPGAs sequentially.

  • FPGA_PCM:

    • This is Parallel Configuration Mode. It enables parallel configuration of FPGAs from daughterboard NAND memory.

    Note

    FPGA is the default mode on Versatile Express LogicTiles.

    FPGA_PCM is the fastest configuration mode. ARM recommends that you use this mode to configure the FPGAs on the daughterboard.

OSCCLKS section

The OSCCLKS section lists the number of programmable clocks and their frequencies. See the application note documentation and the Technical Reference Manual for the daughterboard that is fitted.

Note

OSCCLKS have an operating range of 2MHz-230MHz with a resolution of better than 1%. This means that the actual oscillator frequency is within 1% of the specified frequency. The oscillator stability is 50 ppm.You must not operate clocks outside of the recommended range.

You can change the clock values at run time using the MCC command line interface, see CFG in Table 7.3, or by writing application code to the SYS-CFG registers, see the Motherboard Express μATX Technical Reference Manual.

Note

This does not apply to the custom motherboard.

SCC REGISTERS section

The SCC REGISTERS section lists serial configuration controller registers present on the daughterboard.

The format is SCC: 0xAAA, 12-bit address, 0xDDDDDDDD, 32-bit data.

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