The use of FPGA technology enables us to provide boards containing fully functional, tested examples of the newest Arm processors before any hard silicon devices are available from a foundry.

It is usual for an SMM to be constructed from one or more LogicTile Express boards. A SODIMM memory module is generally included, to provide the system SDRAM since this is not on the motherboard.

An SMM behaves like a Versatile Express CoreTile, which allows it to be mounted on the V2M-P1 motherboard for use as an off-the-shelf development system. PLLs in the FPGA are used to give the highest possible CPU speed for an FPGA implementation. As it is a drop in replacement for a CoreTile Express board, only a single set of off-board AMBA AXI buses are implemented.

SMMs are available in the Versatile Express range for the following Arm processors:


SMM Express for Cortex-R5 SMM Express for Cortex-R7
     
SMM name (short) SMM-R5 SMM-R7
Part number V2S-CR5-1000A V2S-CR7-1000A
PCB part number HBI-0192 HBI-217
Datasheet Datasheet Datasheet
Manuals User Guide User Guide
Processor type Cortex-R5 Cortex-R7
Num CPUs, Speed Dual, 50MHz Dual, 40MHz
Processor Revision r1p2 r0p0
Coprocessors FPU FPU
Hardware required V2F-1XV5 V2F-2XV6
L1 Cache I/D 64KB/64KB 16KB/16KB
L2 Cache N/A N/A
TCM I/D 64KB x 2, per CPU 64KB x 2, per CPU
Memory 16 MB PSRAM 2GB DDR2 SODIMM
Memory speed 50MHz 125MHz
Bus Type AXI AXI
Int Bus Freq 50MHz 40MHz
Ext Bus Freq 25MHz (M), 35MHz (S) N/A
Supported baseboard V2M-P1 V2M-P1

Tool Support

Software Tools for Versatile Express

DS-5 Development Studio fully supports all Arm processors and IP as well as a wide range of third-party tools, operating systems and EDA flows. DS-5 represents a comprehensive range of software tools to create, debug and optimize systems built on Versatile Express boards.

It incorporates DS-5 Debugger, whose powerful and intuitive graphical environment enables fast debugging of bare-metal, Linux and Android native applications. DS-5 Debugger provides pre-defined configurations for LogicTile Express boards, for a quick and convenient way to start software development.

In addition, Streamline performance analyzer simplifies the identification of hot spots in software and load balancing between cores and clusters with a brilliantly intuitive graphical display.

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

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Answered Where do I find presentations and photos from SC'18? 2 votes 2143 views 0 replies Started 1 years ago by John Linford Answer this
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Suggested answer Debug Connection Cause ExecutionTiming Problem on Second Core of Cortex A9 on Zynq 702 MPCore
  • System on Chip (SoC)
  • Cortex-A9
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Suggested answer Keil uVision Error L6218E: Undefined Symbol APBPrescTable (referred from stm32f4xx_hal_rcc.o)
  • Keil
  • uVision
0 votes 2175 views 9 replies Latest 14 hours ago by Westonsupermare Pier Answer this
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Suggested answer Store operations where the cache line is already cached (ACE protocol)
  • AMBA
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  • AXI
  • Interface
2 votes 6177 views 9 replies Latest 18 hours ago by het Answer this
Suggested answer Static Call Graph Details in Keil IDE 0 votes 207 views 2 replies Latest 19 hours ago by MoAli Answer this
Suggested answer My code is not working if i change the address of flash memory , where the code can be loaded and if change the address back to the base address 0x80000000 then it works. Why? 0 votes 7525 views 4 replies Latest yesterday by Ronan Synnott Answer this
Suggested answer How to get an ELF file from Keil C51
  • Keil C51 Dev Tools
0 votes 370 views 1 replies Latest yesterday by Westonsupermare Pier Answer this
Not answered PendSV target secure state 0 votes 48 views 0 replies Started yesterday by Jiameng Answer this
Answered Where do I find presentations and photos from SC'18? Started 1 years ago by John Linford 0 replies 2143 views
Not answered making physical memory pages not cacheable (probabaly by modifying page table entry) Started 10 hours ago by Gol 0 replies 44 views
Suggested answer Debug Connection Cause ExecutionTiming Problem on Second Core of Cortex A9 on Zynq 702 MPCore Latest 11 hours ago by BurakSeker 3 replies 1359 views
Not answered reading data in http client application Started 13 hours ago by giomaca 0 replies 40 views
Suggested answer Keil uVision Error L6218E: Undefined Symbol APBPrescTable (referred from stm32f4xx_hal_rcc.o) Latest 14 hours ago by Westonsupermare Pier 9 replies 2175 views
Not answered STM32F769i-Discovery IP Camera Interface Started 16 hours ago by Kiran bhat 0 replies 64 views
Not answered NXP i.MXRT1064 Stack Corruption using FLEXCAN / LPUART / Systick Interrupts Started 16 hours ago by crevans 0 replies 67 views
Suggested answer Store operations where the cache line is already cached (ACE protocol) Latest 18 hours ago by het 9 replies 6177 views
Suggested answer Static Call Graph Details in Keil IDE Latest 19 hours ago by MoAli 2 replies 207 views
Suggested answer My code is not working if i change the address of flash memory , where the code can be loaded and if change the address back to the base address 0x80000000 then it works. Why? Latest yesterday by Ronan Synnott 4 replies 7525 views
Suggested answer How to get an ELF file from Keil C51 Latest yesterday by Westonsupermare Pier 1 replies 370 views
Not answered PendSV target secure state Started yesterday by Jiameng 0 replies 48 views