A PSA Certified Level 1 Samsung 28FDS eMRAM-enabled IoT Demonstrator
In addition to the Arm IP blocks, the test chip contains peripheral IP from Cadence. For example, QSPI, PWM, I2C or I2S IPs and eMRAM macros, Body-bias generator, and PLL IPs from Samsung Foundry.
It is manufactured in Samsung 28FDS FD-SOI process technology to match the requirement of energy-efficient and secure IoT nodes. This makes the test chip a good model for system development and how to make designing IoT security and energy efficiency easier and faster.
Development platform for PSA
IoT security requires a layered approach across the device and network to protect the entire IoT network. The Platform Security Architecture (PSA) framework enables IoT designers to make security an integral part of their design from the start by following a four-step process of; analyze, architect, implement and certify. Musca-S1 test chip architecture demonstrates how to design PSA-ready systems for PSA Certified accreditation, providing a tried, and tested development platform for secure IoT devices.
TrustZone for Armv8-M reference system
The subsystem architecture at the center of the Musca-S1 test chip expands the Arm TrustZone isolation outside of the processor, throughout the system and is used by all the ecosystem surrounding the new Armv8-M processors.
Embedded security with CryptoCell
Isolation is the secret to get secure systems. In addition to a Root-of-Trust, the Arm CryptoCell IP brings an extra level of security for key handling, lifecycle management, encryption, authentication, and many other crypto services.
Energy Efficiency with 28FDS, Body-Biasing, eMRAM and dual asymmetric Cortex-M33
The processing architecture of the subsystem at the heart of the Musca-S1 test chip ensures that processing performance is available when you need it, but saves energy when processing is not required. Musca-S1 test chip board deploys new eMRAM technology for reliable, low-power and secure device development through secure memory implementation. eMRAM technology offers advantages over traditional embedded flash (eFlash) memory technology, as it can easily scale below 40nm process technology, giving SoC designers more flexibility to scale their memory needs based on the memory and power requirements of various use-cases.