Musca-S1 Test Chip Board

About Musca-S1

The Musca-S1 implementation of SSE-200 subsystem on Samsung Foundry 28FDS is ready to be used to form the core processing element of mainstream IoT devices with secure PSA Root-of-Trust (RoT). Musca-S1 can be used to prototype secure boot, on-chip storage, execution, and network device management through TF-M, Mbed OS, and Pelion IoT platform integration.

Musca-S1 test chip demonstrates a combination of on-chip power control, Samsung Foundry’s Reverse Body Biasing (RBB) and eMRAM non-volatile memory power shutdown, allowing for testing and evaluation of new classes of highly energy-efficient, controlled IoT devices.

By combining Arm IP and software solutions on a single board, IoT designers can test and evaluate Arm end-to-end secure IoT solution, showcasing highly energy-efficient and secure IoT at scale. The Musca-S1 test chip board can further reduce costs and time-to-market by giving designers the flexibility to repurpose the reference design for future products.

Key product highlights

Musca-S1 is a test chip built from several Arm IP components, these include:

• Arm Cortex-M33 processor
• Arm Corstone-200 containing:
  • CoreLink SSE-200 Subsystem
  • CoreLink SIE-200 system IP
  • Cortex-M System Design Kit components
• Arm CoreSight SoC-400 debug infrastructure
• Arm TrustZone for Cortex-M
  • CryptoCell-312 Security IP

A PSA Certified Level 1 Samsung 28FDS eMRAM-enabled IoT Demonstrator

In addition to the Arm IP blocks, the test chip contains peripheral IP from Cadence. For example, QSPI, PWM, I2C or I2S IPs and eMRAM macros, Body-bias generator, and PLL IPs from Samsung Foundry.

It is manufactured in Samsung 28FDS FD-SOI process technology to match the requirement of energy-efficient and secure IoT nodes. This makes the test chip a good model for system development and how to make designing IoT security and energy efficiency easier and faster.

Key features

Development platform for PSA

IoT security requires a layered approach across the device and network to protect the entire IoT network. The Platform Security Architecture (PSA) framework enables IoT designers to make security an integral part of their design from the start by following a four-step process of; analyze, architect, implement and certify. Musca-S1 test chip architecture demonstrates how to design PSA-ready systems for PSA Certified accreditation, providing a tried, and tested development platform for secure IoT devices.

TrustZone for Armv8-M reference system

The subsystem architecture at the center of the Musca-S1 test chip expands the Arm TrustZone isolation outside of the processor, throughout the system and is used by all the ecosystem surrounding the new Armv8-M processors.

Embedded security with CryptoCell

Isolation is the secret to get secure systems. In addition to a Root-of-Trust, the Arm CryptoCell IP brings an extra level of security for key handling, lifecycle management, encryption, authentication, and many other crypto services.

Energy Efficiency with 28FDS, Body-Biasing, eMRAM and dual asymmetric Cortex-M33

The processing architecture of the subsystem at the heart of the Musca-S1 test chip ensures that processing performance is available when you need it, but saves energy when processing is not required. Musca-S1 test chip board deploys new eMRAM technology for reliable, low-power and secure device development through secure memory implementation. eMRAM technology offers advantages over traditional embedded flash (eFlash) memory technology, as it can easily scale below 40nm process technology, giving SoC designers more flexibility to scale their memory needs based on the memory and power requirements of various use-cases.

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.