Getting started

The Juno development board is an open, vendor-neutral, Armv8-A development platform that supports an out-of-the-box Linux software package delivered by Linaro. The Juno development board provides an excellent environment for the development of the next-generation system-on-chip designs. A range of plug-in expansion options enables hardware and software applications to be developed and debugged.

Juno hardware

  • Arm Cortex-A72 MPCore (Juno r2)
  • Arm Cortex-A53
  • Arm big.LITTLE technology
  • Arm Mali graphics processor for 3D Graphics Acceleration and GP-GPU compute
  • 4-lane Gen 2.0 PCI-Express
  • A SoC architecture aligned with Level 1 (Server) Base System Architecture

Juno Software

  • System Control Processor (SCP) Firmware
    • System initialisation, cold boot flow and controls clocks, voltage, power gating.
    • Delivered as binary via Linaro with public programmers interface
  • Application Processor (AP) Software – all delivered as source via Linaro
    • Arm Trusted Firmware – supporting PSCI power controls and trusted execution environments
    • Choice of UEFI or U-Boot firmware
    • Linux – support for both latest kernel and Linaro Stable Kernel which includes Mali GPU drivers and Android patch set
      • Includes big.LITTLE scheduling and Intelligent Power Allocation support from Arm
    • Linaro supported Linux filesystems including:
    • Busybox
    • OpenEmbedded (yocto)
    • Android (Linaro Confectionary Release) – contains user-space driver for the Mali GPU

    Fully described on the Arm development platforms connected community page.


Software development on Juno

  • Armv8-A AArch64 kernel and tools development for Cortex-A processor family
  • PCI-Express software development
  • Secure OS and Hypervisors through Arm Trusted Firmware
  • Expansion using a LogicTile Express that connects directly to the platform
  • 3D graphics and GPU compute with native big.LITTLE and Mali support
  • Middleware and file systems porting and optimisation to 64-bit
  • Real-time debug, trace and performance tuning with CoreSight technology


Juno r2 
 Target  Platform for big.LITTLE development with big.LITTLE and PCI-Express 
 big cluster Cortex-A72 r0p0eac
 LITTLE cluster Cortex-A53 r0p3
 CCI-400 r1p3
 NIC-400 r0p2
 TZC-400 r0p1 
 STM STM-500 r0p1 
 FPGA support Fully coherent 
 PCI-Express support Yes, 4 lanes plus GbEthernet & SATA

Juno expansion

A range of plug-in expansion options enables hardware and software applications to be developed and debugged.

Arm LogicTile Express Expansion

The Juno Arm Development Platform can be expanded by adding a LogicTile Express development board. This enables the addition of user logic to the system. The FPGA board connects to the platform using master and slave Thin Links, which enables off-chip communication.

Application Note AN415 shows how to enable connection of an LogicTile Express to the Juno Development Platform and is available for download here.

The Juno r2 can also be expanded using the 4 Gen 2.0 PCI-Express slots.

PRO DESIGN proFPGA FPGA Expansion

The Juno platform supports PRO DESIGN Electronics proFPGA uno, duo and quad Prototyping solution, offering a larger capacity FPGA solution beyond LogicTile Express. The proFPGA product family is a complete, scalable and modular multi-FPGA prototyping solution consisting of different types of motherboards, various Xilinx Virtex® FPGA modules based on the latest Virtex UltraScale™ technology and a portfolio of interconnection boards/cables, as well as a large range of daughter boards including memory boards and high-speed interface boards. This solution is supported by all Juno variants and an example Application Note AN499 is available as a starting point for an FPGA design implementation. A short video showing the mechanical assembly instructions is available here.

Juno proFPGA picture

Synopsys® HAPS FPGA Expansion

The Juno platform supports the Synopsys HAPS FPGA solution offering a range of capacity FPGA solution in addition to LogicTile Express. HAPS FPGA-based physical prototyping systems include an integrated hardware and software tool flow for design planning, FPGA synthesis and debug. The HAPS ProtoCompiler software, which has built-in knowledge of the HAPS system architecture, automates partitioning to map IP blocks to complete subsystems and SoCs. Juno is supported by the HAPS-80, HAPS-70 and HAPS-DX series. More information on Synopsys's FPGA range is available HAPS FPGA.

HAPS-FPGA + Juno

S2C’s Prodigy FPGA Expansion

The Juno Platform supports the S2C Prodigy FPGA Logic Module Systems to  increase scalability of FPGA prototyping for designs based on Armv8-A. The Prodigy Interface Module for Juno effectively bridges the software development environment to the S2C’s Prodigy Logic Modules for prototyping custom logic blocks alongside the Arm processor. The Prodigy Interface Module for Juno works with the Prodigy Complete Prototyping Platform that includes advanced capabilities for design partitioning, prototype configuration, multi-FPGA debug, and the ability to scale beyond 1.5B gates utilizing the Prodigy Cloud Cube architecture.

Prodigy Interface Module Kit for Arm Juno includes the following:

  • One Prodigy Interface Module for Juno
  • One I/O loopback test module for Arm Juno
  • One 8GB DDR4 Pre-tested SO-DIMM Memory Module
  • One 400mm Prodigy Cable
  • One reference design for Juno, tutorial guide and application note

The kit also includes a complete easy set up reference design that shows:

  • Comprehensive self-testing between the Prodigy Logic Modules and the Juno Arm Development Platform
  • Expanded FPGA capacity
  • Early porting of OS kernel or driver code for Armv8-A processors
  • High-speed DDR4 memory access between the Logic Module(s) and Juno Arm Development Platform

More information on S2C Prodigy Complete FPGA Prototyping Platform offerings is available here.

ARM Juno S2C adapter


Tool support

With out-of-the-box support for the Juno Arm Development Platform, Arm Development Studio is the complete tool suite for Arm, including Armv8-A. Enabling code generation, debug, trace and optimization of software from bare-metal to userspace, Arm Development Studio has been developed alongside the Armv8-A architecture to help take full advantage of Arm’s highest performance processors.

It offers Arm Debugger for Linux and Android, along with a range of RTOSs, keeping track of threads and processes across multicluster and big.LITTLE configurations is intuitive. System optimization is made easier with excellent support for advanced debug and trace services, whilst Streamline helps identify bottlenecks in CPU and Mali GPU, which can be tracked down to individual functions or lines of source code.



Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

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0 votes 494 views 2 replies Latest 12 hours ago by sska.73 Answer this
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  • System on Chip (SoC)
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Suggested answer Keil uVision Error L6218E: Undefined Symbol APBPrescTable (referred from stm32f4xx_hal_rcc.o)
  • Keil
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0 votes 2261 views 9 replies Latest yesterday by Westonsupermare Pier Answer this
Not answered STM32F769i-Discovery IP Camera Interface 0 votes 80 views 0 replies Started yesterday by Kiran bhat Answer this
Answered Where do I find presentations and photos from SC'18? Started 1 years ago by John Linford 0 replies 2146 views
Not answered interfacing STM32 F401re with mcp2515 Started 6 hours ago by sunil_reddy 0 replies 8 views
Not answered Pros and cons of activating cache in stm32F7 Started 6 hours ago by Marzi 0 replies 13 views
Suggested answer Static Call Graph Details in Keil IDE Latest 11 hours ago by MoAli 4 replies 378 views
Not answered CHI protocol cache line states Started 11 hours ago by S_Seth 0 replies 59 views
Answered How to configure GIC in Cortex-R52 for FreeRTOS? Latest 12 hours ago by sska.73 2 replies 494 views
Not answered making physical memory pages not cacheable (probabaly by modifying page table entry) Started 22 hours ago by Gol 0 replies 278 views
Suggested answer Debug Connection Cause ExecutionTiming Problem on Second Core of Cortex A9 on Zynq 702 MPCore Latest 22 hours ago by BurakSeker 3 replies 1386 views
Suggested answer How to access memory more than 4GB by using 32bit ISA? Latest 23 hours ago by smithclarkson001 4 replies 348 views
Not answered reading data in http client application Started yesterday by giomaca 0 replies 60 views
Suggested answer Keil uVision Error L6218E: Undefined Symbol APBPrescTable (referred from stm32f4xx_hal_rcc.o) Latest yesterday by Westonsupermare Pier 9 replies 2261 views
Not answered STM32F769i-Discovery IP Camera Interface Started yesterday by Kiran bhat 0 replies 80 views