Arm Neoverse N1 sideview of board

Overview

The Neoverse N1 System Development Platform (SDP) is an N1 CPU-based development platform for hardware prototyping, software development, system validation, and performance profiling or tuning.

N1 SDP platform consists of a hardware board with Neoverse N1 SoC running a complete Armv8.2-A open-source software stack that is available through GitHub and other hosting sites such as Linaro. N1 SoC has been developed using 7nm manufacturing process targeting CPU frequency of 2.6GHz. The following image shows a side view of the Neoverse N1 board connectivity for plugging in external peripherals.

Neoverse N1 SDP provides an excellent environment for developing the next generation of System on Chip designs. Through a range of plug-in options, hardware and software applications can be developed and debugged.

N1 SoC supports full-speed operation for the N1 CPUs, fully sized caches, and generous amounts of memory bandwidth with the latest optimized system IP. Therefore, realistic workload analyses can be performed to optimize software performance for production environments. N1 SDP is also one of the earliest available boards for connecting CCIX-enabled FPGAs or custom ASICs for developing new software models for coherent acceleration use cases.


Specifications

The following block diagram shows the Neoverse N1 SoC and its major IP components.

Neoverse N1 block diagram

N1 SDP delivers to developers an Armv8.2-A development platform with:

  • Two dual-core Neoverse N1 CPU clusters
  • N1 backplane fabric comprising coherent mesh interconnect (CMN-600), I/O Memory Management Unit (MMU-600), and Generic Interrupt Controller (GIC-600)
  • Real-time debug and trace capability using CoreSight SoC-400
  • Support for dual-channel DDR4-2667 memory
  • Support for x16 PCIe/CCIX Gen4 links for coherent chip-to-chip attach through CCIX
  • An SoC architecture compliant with Server Based System Architecture (SBSA) v3 and Server Based Boot Requirements (SBBR)

The N1 SDP software stack available through open-source repositories, delivers to developers an out-of-the box Linux software package running:

  • Trusted Firmware-A (TF-A)
  • AArch64 Linux kernel with supporting file systems and drivers including those for PCIe/CCIX, chip-to-chip boot, and symmetric multi-processing (SMP)
  • Universal Extensible Firmware Interface (UEFI) and Advanced Configuration and Power Interface (ACPI) support

The N1 SDP enables:

  • AArch64 kernel and tools development for Neoverse N1 platform
  • PCIe Gen4 and CCIX ecosystem development
  • Secure boot, OS, and hypervisor development through Trusted Firmware-A
  • Development of coherent acceleration use cases using a CCIX compatible FPGA board that connects over CCIX link to the Neoverse N1 board
  • Real-time debug using P-JTAG and 32-bit trace debug

Features

Neoverse N1 SDP contains the following hardware and software features:

Hardware features

  • Dual-core, dual-cluster SMP configuration with a total of 4 N1 CPUs
  • N1CPU
    • 2.6GHz operating speed
    • Caches (per core): L1 64kB instruction cache and data cache, 1MB private L2 cache
    • Caches (shared): shared 2MB L3 between all cores, 8MB shared system level cache (SLC), both can be configured down to size zero
  • Internal CMN-600 interconnect operating up to 2GHz
  • GIC-600 and MMU-600 for interrupt management and I/O virtualization support
  • 2 x 72-bit DMC-620 memory controller for dual channel DDR4 2667MHz memory
  • Two Cortex-M7 CPUs functioning as System Control Processor (SCP) and Management Control Processor (MCP) for supporting event logging, power and device management
  • CoreSight SoC-400 functional debug and trace capability

Board expansion support with corresponding external ports

  • 1x CCIX Gen4 x16 port
    • Support for one x16 CCIX capable adapter card
  • 1x PCIe x16 Gen3 link to 48-lane switch with downstream slots and peripherals
    • x16 PCIe Gen3
    • x8 PCIe Gen3
    • x1 PCIe Gen3
    • x1 Gigabit Ethernet
    • x1 SATA III
    • x1 USB 3.0
  • 32-bit MIPI-60 trace port, JTAG debug port plus Arm CoreSight 20 JTAG connector for debug only
  • Optional PCIe Gen3 riser card kit to connect two N1 SDP boards back-to-back over CCIX for Symmetric Multi-Threading (SMT) operation

Software features

The following are the key software components available from Arm with the N1 SDP:

  • SCP Firmware
    • System initialization, cold boot flow, control clocks and, device management
  • Trusted Firmware-A
    • Provides a reference implementation of Secure world software for Armv8-A, including a Secure monitor executing at Exception level 3 (EL3)
  • 64-bit Linux drivers including those for PCIe/CCIX/ SMP and more.
  • UEFI and ACPI support
  • Scripts for downloading various open-source components including Linux kernel

The following image is a top view of the Neoverse N1 board, showing an SoC chip and associated board components:

Arm Neoverse N1 top view of board