Getting Started

Neoverse reference designs provide useful resources with best practices on how to integrate a Neoverse compute subsystem within a larger SoC. These compute subsystems are targeted at addressing requirements for specific applications in the cloud-to-edge infrastructure markets including servers, edge compute nodes, networking-storage-security offloads, mezzanine cards, 5G stations and access points. 


Neoverse N1 hyperscale reference design

The Neoverse N1 hyperscale reference design details the integration of a high core count server-class SoC subsystem using the Neoverse N1 CPU, CMN-600 coherent mesh interconnect and supporting system IP.

Diagram for the Neoverse N1 hyperscale reference design.

  • 64x Neoverse N1 CPUs, each with 1MB private L2, providing 64 threads of parallel execution
  • 8x8 coherent mesh interconnect (CMN-600) configuration with 64MB of shared system level cache
  • CPUs connected directly to the mesh in dual-core configurations for lowest latency
  • 4x CCIX links for multi-socket, chiplets and accelerator attached configurations
  • 8x memory channels supporting DDR4-3200
  • GIC-600 and CoreSight SoC-400 interfacing over the mesh
  • MMU-600 system MMU and NIC-450 non-coherent interconnect integration with PCIe Gen4 support
  • Fully compliant with Arm ServerReady 1.0 specification

Neoverse N1 edge reference design

The Neoverse N1 edge reference design details the integration of a moderate core count edge server SoC subsystem with the Neoverse N1 CPU and CMN-600 mesh interconnect.

Neoverse N1 Edge Reference Design diagram 

  • 8x Neoverse N1 CPUs, each with 512kB private L2, providing 8 threads of parallel execution
  • 4x2 CMN-600 configuration with 8MB of shared system level cache
  • CPUs are connected to the mesh through quad-core clusters with 2MB shared L3
  • 4x CCIX links to support chiplet and accelerator attached configurations
  • 2x memory channels supporting DDR4-3200
  • GIC-600 generic interrupt controller and CoreSight SoC-400 debug and trace IP interfacing over the mesh
  • MMU-600 system MMU and NIC-450 non-coherent interconnect integration with PCIe Gen4 support
  • Fully compliant with Arm ServerReady 1.0 specification

Neoverse E1 edge reference design

The Neoverse E1 edge reference design details the integration of a moderate core count high data throughput SoC subsystem with the Noeverse E1 CPU and CMN-600 mesh interconnect.

Neoverse E1 Edge Reference Design diagram 

  • 16x Neoverse E1 CPUs, each with 256kB private L2, providing 32 threads of parallel execution
  • 4x2 CMN-600 mesh configuration with 8MB of shared system level cache
  • CPUs are connected to the mesh through octa-core clusters with 2MB shared L3
  • 4x CCIX links to support chiplet and accelerator attached configurations
  • 2x memory channels supporting DDR4-3200
  • GIC-600 generic interrupt controller and CoreSight SoC-400 debug and trace IP interfacing over the mesh
  • MMU-600 system MMU and NIC-450 non-coherent interconnect integration with PCIe Gen4 support
  • Fully compliant with Arm ServerReady 1.0 specification

Request information

Want to know more about system guidance? Contact Arm today.

Contact us

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses Open a support case

Community Blogs

Community Forums

Answered Where do I find presentations and photos from SC'18? 1 votes 894 views 0 replies Started 5 months ago by John Linford Answer this
Not answered what action will be performed by the master based on the read and write responce in axi 4?
  • AXI
  • AXI4
0 votes 11 views 0 replies Started 5 hours ago by Hem Patel Answer this
Not answered Object detection 0 votes 10 views 0 replies Started 5 hours ago by Martin Peniak Answer this
Suggested answer Cortex-A Support in MacOS
  • Cortex-A
  • GNU
0 votes 460 views 4 replies Latest 6 hours ago by Ron Aaron Answer this
Not answered Trigger a Software Interrupt 0 votes 12 views 0 replies Started 6 hours ago by Aquox Answer this
Suggested answer Modify SP register and PC register in Cortex-M1 using Keil
  • R15 (PC Program Counter)
  • Cortex-M1
  • R13 (SP Stack Pointer)
  • Keil
0 votes 105 views 3 replies Latest 10 hours ago by 42Bastian Schick Answer this
Answered Where do I find presentations and photos from SC'18? Started 5 months ago by John Linford 0 replies 894 views
Not answered what action will be performed by the master based on the read and write responce in axi 4? Started 5 hours ago by Hem Patel 0 replies 11 views
Not answered Object detection Started 5 hours ago by Martin Peniak 0 replies 10 views
Suggested answer Cortex-A Support in MacOS Latest 6 hours ago by Ron Aaron 4 replies 460 views
Not answered Trigger a Software Interrupt Started 6 hours ago by Aquox 0 replies 12 views
Suggested answer Modify SP register and PC register in Cortex-M1 using Keil Latest 10 hours ago by 42Bastian Schick 3 replies 105 views