Neoverse V1 reference design
The Neoverse V1 reference design details the integration of a high core count server-class SoC subsystem using the Neoverse V1 CPU and CMN-650 mesh interconnect.
4x Chiplets, each with:
- 32x Neoverse V1 CPUs each with 1MB private L2 providing 32 threads of parallel execution.
- 6x6 coherent mesh interconnect (CMN-650) configuration with 32MB of shared system level cache.
- CPUs connected directly to the mesh in dual-core configurations for lowest latency.
- 6x CCIX D2D links for 2-4 SMP chiplets and 2x CCIX external links for attaching accelerators.
- 4 pairs of memory channels for 4x DDR5-4800.
- 8 memory ports for dual channel HMB2e.
- GIC-600 and CoreSight SoC-600 interfacing over the mesh.
- MMU-600 system MMU and NIC-450 non-coherent interconnect integration with PCIe Gen4 support.
- Fully compliant with Arm ServerReady 2.0 specification, SBSA level 4.
Neoverse V1 fixed virtual platform model
The Neoverse RD-V1 bundle contains software accurate FVP (Fast) model of a quad-chiplet with reduced core count to demonstrate multi-chiplet initialization from a single shared external flash boot image.
- 4x Neoverse V1 cores per chiplet.
- 3x pairs of SMP and CCIX links attach directly to the neighboring chiplets.
- Selectable pre-boot configuration of 1, 2, or 4 chiplets.
- Management and System Control Processors boot each chiplet independently from shared flash boot image and sync with designator manager.
- Internal and board level peripherals based on the Juno Arm Development Platform.
- Management and System Control Processor firmware for power, clocks, BIST, initial configuration and OS entry point.
- Linux kernel and Juno ADP device drivers to support multi-processor multi-chiplet NUMA optimizations and common peripherals.
The Neoverse V1 fixed virtual platform model and associated open-source software downloads and resources are available from the Arm Ecosystem FVPs page. To assist you working with them, view the Neoverse V1 reference design Software Developer Guide.
Neoverse N2 reference design
The Neoverse N2 reference design details the integration of an infrastructure-class SoC subsystem using the Neoverse N2 CPU, CMN-700 coherent mesh interconnect and supporting system IP. This reference design targets 5G, networking and scale-out cloud.
- 32x Neoverse N2 CPUs, each with 1MB private L2, providing 32 threads of parallel execution.
- 6x6 coherent mesh interconnect (CMN-700) configuration with 32MB of shared system-level cache.
- CPUs connected directly to the mesh in dual-core configurations for low latency.
- 4x/8x memory channels supporting DDR5-5600.
- GIC-700 and CoreSight SoC-600 interfacing over the mesh.
- MMU-700 system MMU and NIC-450 non-coherent interconnect integration with PCIe Gen5 support.
- Compliant with Arm Server Base System Architecture (SBSA) 6.0.
Neoverse N1 hyperscale reference design
The Neoverse N1 hyperscale reference design details the integration of a high core count server-class SoC subsystem using the Neoverse N1 CPU, CMN-600 coherent mesh interconnect and supporting system IP.
- 64x Neoverse N1 CPUs, each with 1MB private L2, providing 64 threads of parallel execution
- 8x8 coherent mesh interconnect (CMN-600) configuration with 64MB of shared system level cache
- CPUs connected directly to the mesh in dual-core configurations for lowest latency
- 4x CCIX links for multi-socket, chiplets and accelerator attached configurations
- 8x memory channels supporting DDR4-3200
- GIC-600 and CoreSight SoC-400 interfacing over the mesh
- MMU-600 system MMU and NIC-450 non-coherent interconnect integration with PCIe Gen4 support
- Fully compliant with Arm ServerReady 1.0 specification
Neoverse N1 edge reference design
The Neoverse N1 edge reference design details the integration of a moderate core count edge server SoC subsystem with the Neoverse N1 CPU and CMN-600 mesh interconnect.
- 8x Neoverse N1 CPUs, each with 512kB private L2, providing 8 threads of parallel execution
- 4x2 CMN-600 configuration with 8MB of shared system level cache
- CPUs are connected to the mesh through quad-core clusters with 2MB shared L3
- 4x CCIX links to support chiplet and accelerator attached configurations
- 2x memory channels supporting DDR4-3200
- GIC-600 generic interrupt controller and CoreSight SoC-400 debug and trace IP interfacing over the mesh
- MMU-600 system MMU and NIC-450 non-coherent interconnect integration with PCIe Gen4 support
- Fully compliant with Arm ServerReady 1.0 specification
Neoverse E1 edge reference design
The Neoverse E1 edge reference design details the integration of a moderate core count high data throughput SoC subsystem with the Noeverse E1 CPU and CMN-600 mesh interconnect.
- 16x Neoverse E1 CPUs, each with 256kB private L2, providing 32 threads of parallel execution
- 4x2 CMN-600 mesh configuration with 8MB of shared system level cache
- CPUs are connected to the mesh through octa-core clusters with 2MB shared L3
- 4x CCIX links to support chiplet and accelerator attached configurations
- 2x memory channels supporting DDR4-3200
- GIC-600 generic interrupt controller and CoreSight SoC-400 debug and trace IP interfacing over the mesh
- MMU-600 system MMU and NIC-450 non-coherent interconnect integration with PCIe Gen4 support
- Fully compliant with Arm ServerReady 1.0 specification
