Neoverse N1 hyperscale reference design
The Neoverse N1 hyperscale reference design details the integration of a high core count server-class SoC subsystem using the Neoverse N1 CPU, CMN-600 coherent mesh interconnect and supporting system IP.
- 64x Neoverse N1 CPUs, each with 1MB private L2, providing 64 threads of parallel execution
- 8x8 coherent mesh interconnect (CMN-600) configuration with 64MB of shared system level cache
- CPUs connected directly to the mesh in dual-core configurations for lowest latency
- 4x CCIX links for multi-socket, chiplets and accelerator attached configurations
- 8x memory channels supporting DDR4-3200
- GIC-600 and CoreSight SoC-400 interfacing over the mesh
- MMU-600 system MMU and NIC-450 non-coherent interconnect integration with PCIe Gen4 support
- Fully compliant with Arm ServerReady 1.0 specification
Neoverse N1 edge reference design
The Neoverse N1 edge reference design details the integration of a moderate core count edge server SoC subsystem with the Neoverse N1 CPU and CMN-600 mesh interconnect.
- 8x Neoverse N1 CPUs, each with 512kB private L2, providing 8 threads of parallel execution
- 4x2 CMN-600 configuration with 8MB of shared system level cache
- CPUs are connected to the mesh through quad-core clusters with 2MB shared L3
- 4x CCIX links to support chiplet and accelerator attached configurations
- 2x memory channels supporting DDR4-3200
- GIC-600 generic interrupt controller and CoreSight SoC-400 debug and trace IP interfacing over the mesh
- MMU-600 system MMU and NIC-450 non-coherent interconnect integration with PCIe Gen4 support
- Fully compliant with Arm ServerReady 1.0 specification
Neoverse E1 edge reference design
The Neoverse E1 edge reference design details the integration of a moderate core count high data throughput SoC subsystem with the Noeverse E1 CPU and CMN-600 mesh interconnect.
- 16x Neoverse E1 CPUs, each with 256kB private L2, providing 32 threads of parallel execution
- 4x2 CMN-600 mesh configuration with 8MB of shared system level cache
- CPUs are connected to the mesh through octa-core clusters with 2MB shared L3
- 4x CCIX links to support chiplet and accelerator attached configurations
- 2x memory channels supporting DDR4-3200
- GIC-600 generic interrupt controller and CoreSight SoC-400 debug and trace IP interfacing over the mesh
- MMU-600 system MMU and NIC-450 non-coherent interconnect integration with PCIe Gen4 support
- Fully compliant with Arm ServerReady 1.0 specification
