Arm Debugger Manual Configuration Tutorial

Tutorial on how to manually configure a platform configuration using Arm Development Studio's Platform Configuration Editor (PCE)


Overview Understanding CoreSight Understanding a target's debug and trace infrastructure Set up the platform configuration manually Manually configuring a platform configuration for debug Manually configuring a platform configuration for trace

Manually configuring a platform configuration for debug

In this section, we manually create a platform configuration for the target described in the Set up the platform configuration manually section.  We focus on creating a platform configuration we can debug only first, so that we know we have a working configuration before we move on to adding trace capability in the next section.

Below is a block diagram of the debug-related devices for the board we are manually configuring:Diagram of the example target's debug infrastructure

     

    The debug-specific details of this target are:

  • All the target’s CoreSight devices are behind a DP.
  • The DP has three APs:
    • An AXI-AP which enables direct access to the board’s system memory via the DP.
    • An APB-AP which grants access to the CoreSight components for the Cortex-A72 and Cortex-A53 clusters.This AP has a ROM table.
    • An AHB-M-AP which grants access to the Cortex-M3 and its associated CoreSight devices.This AP has a ROM table.
  • A Cortex-A72 cluster containing 2 Cortex-A72 cores.
  • A Cortex-A53 cluster containing 4 Cortex-A53 cores.
  • Each core has an associated CTI.

Each cluster has a Cross Trigger Matrix (CTM) to connect that cluster’s CTIs together.

A CTM to connect the cluster CTMs together to enable cross-cluster synchronization.

It is important to note that the Cortex-M3 associated CTI is not connected to either CTM, so synchronizing debug operations between the clusters and the Cortex-M3 is not possible.

We now start adding devices to the platform configuration.

Add a DP and APs to the platform configuration

In this section, we add a DP, an AXI-AP, and an APB-AP to the platform configuration.

  1. Click on Devices in the SDF file.

    A SDF file with an empty Devices list

  2. Click Toggle Devices Panel.

    Toggling the Devices Panel

  3. Click DebugPort > ARMCS-DP.

    Selecting an ARMCS-DP

  4. Drag ARMCS-DP to Devices.

    This adds a ARMCS-DP device to the Devices list:

    Adding an ARMCS-DP

    Repeat a similar process for every device added.

  5. Add an AXI-AP to the ARMCS-DP.

    Add a CSMEMAP (0: AXI-AP) – APv1 to the ARMCS-DP:

    Adding a CSMEMAP (AXI-AP) - AP1

  6. Click on CSMEMAP (0: AXI-AP) under ARMCS-DP.

    There are certain settings which must be correct for Arm Debugger to connect and debug the board.

    • CORESIGHT_AP_INDEX
      • The AP’s index number on the DP.
    • AP_VERSION
      • The version of the architecture the AP implements.
    • AP_TYPE
      • The type of the AP for the MEM-AP.
    • Optional, ROM_TABLE_BASE_ADDRESS
      • The base address of the ROM table for the AP.
      • This is optional as setting the ROM table is not necessary for manual configuration.You want to set this if:
        • The ROM table base address reported by the target is incorrect.
        • You are going to auto-detect the devices attached to an AP after manually adding the AP.

    For our board, the details for AP0 are:

    • CORESIGHT_AP_INDEX is 0x0.
    • AP_VERSION is APv1.
    • AP_TYPE is AXI-AP.
    • ROM_TABLE_BASE_ADDRESS is left empty as there is no ROM table on this AP.

    Setting up the CSMEMAP (AXI-AP) - AP1

  7. Add an APB-AP to the ARMCS-DP.
  8. Add a CSMEMAP (1: APB-AP) – APv1 to the ARMCS-DP:

    Adding a CSMEMAP (APB-AP) - AP1

     

  9. Click on CSMEMAP (1:APB-AP) under ARMCS-DP.

    For our board, the details for AP1 are:

    • CORESIGHT_AP_INDEX is 0x1.
    • AP_VERSION is APv1.
    • AP_TYPE is APB-AP.
    • ROM_TABLE_BASE_ADDRESS is 0x80000000.

Note on enumerating APs

After adding a DP to the platform configuration, you can choose to use the PCE auto-detection process to enumerate the DP’s APs rather than adding the APs manually.

To enumerate the APs:

  1. In the SDF under Debug Adaptor > Autodetect > Probe Connection, set the Connection Address to the correct debug unit type and browse for the TCP or USB address of the debug unit connected to the target.
  2. Under Devices, right-click on the DP.
  3. Select Enumerate APs.

All the found APs appear under the DP.

In this tutorial, the APs are added manually.

Note on reading ROM table(s)

After adding an AP to the platform configuration, you can choose to use the PCE auto-detection process to read the AP’s ROM table(s).  Reading the ROM table(s) has PCE read each ROM table entry, determine the devices listed, and add the determined devices to the platform configuration.  This process replaces having to manually add the AP devices.

To read the AP’s ROM table(s):

  1. In the SDF under Debug Adaptor > Autodetect > Probe Connection, set the Connection Address to the correct debug unit type and browse for the TCP or USB address of the debug unit connected to the target.
  2. Under Devices, right-click on an AP.
  3. Select Read CoreSight ROM Tables.

All the determined CoreSight devices appear under the AP.

In this tutorial, the AP devices are added manually.

Add debug devices and component connections to the platform configuration

In this section, we add the below to the platform configuration:

  1. A Cortex-A72 core.
  2. A CTI for the Cortex-A72 core.
  3. A component connection between the Cortex-A72 core and its CTI.
  4. The rest of the debug-related devices and component connections.

This section also covers the generated platform configuration debug activities such as bare-metal and SMP debug connections.  Additionally, this section lists good tests to check whether the platform configuration allows you to successfully debug a target with the Arm Debugger.

  1. In the Devices Panel, select CoreExecutable > Cortex-A72 and drag it to CSMEM-AP_1.

    Add a Cortex-A72 to CSMEMAP_1:

    Adding a Cortex-A72

  2. Click on Cortex-A72 under CSMEMAP_1.

    There are certain core settings which must be correct for Arm Debugger to connect and debug the core.

    • CORESIGHT_BASE_ADDRESS
      • The lower 32-bits of the CoreSight base address for the core.
    • CORESIGHT_BASE_ADDRESS_MSW
      • The higher 32-bits of the CoreSight base address for the core.
    • CTI_CORESIGHT_BASE_ADDRESS
      • The CoreSight base address for the CTI associated with the core.
    • CTI_SYNCH_START
      • Whether the CTI can be used for synchronizing execution.

    For our board, the details for the first Cortex-A72 are:

    • CORESIGHT_BASE_ADDRESS is 0x82010000.
    • CORESIGHT_BASE_ADDRESS_MSW is 0x0.
    • CTI_CORESIGHT_BASE_ADDRESS is 0x82020000.
    • CTI_SYNCH_START is True as the core has an associated CTI.
  3. Add a CTI for Cortex-A72.

    Add a CTI to the CSMEMAP_1:

    Adding a CSCTI

     

  4. Click on CTI under Cortex-A72.

    There are certain CTI settings which must be correct for Arm Debugger to make use of the CTI for synchronous execution.

    • CORESIGHT_BASE_ADDRESS
      • The lower 32-bits of the CoreSight base address for the CTI.
    • CORESIGHT_BASE_ADDRESS_MSW
      • The higher 32-bits of the CoreSight base address for the CTI.
    • SYNCH_START_ENABLE
      • Enables synchronized execution.For example, use the CTI to start and stop the associated core.
    • SYNCH_START_CHANNEL
      • Which CTI channel is associated with starting core execution.

    For our board, the details for the first CTI are:

    • CORESIGHT_BASE_ADDRESS is 0x82020000.
    • CORESIGHT_BASE_ADDRESS_MSW is 0x0.
    • SYNCH_START_ENABLE is True as CTI is used for synchronous core starting.
    • SYNCH_START_CHANNEL is 1 as synchronous starting is linked to CTI channel 1.
  5. Click Devices to view the details of the devices you have added.

    List of current devices in the Devices tab

    To debug a target, Arm Debugger must know how the components are connected.  We add this connection information, the CoreSight topology, in the Component Connections tab.

  6. Select the Component Connections tab.

    We must add a component connection detailing how the Cortex-A72 is connected to its associated CTI.

  7. Click Add Link.

    The Add Link view lets you enter the connected Master and Slave components using the drop-downs and any additional connection details.

    In this case:

    • The Master is the Cortex-A72.
    • The Slave is the CSCTI.
    • The Trigger DBGRESTART is 1. Trigger DBGRESTART is the CTI channel that core start is connected to.

    Adding a component connection between the Cortex-A72 and the CSCTI

     

  8. Click OK.

    The created link appears in the Component Connections tab:

    Connection Component tab after CSCTI is added

    You now have all the information you to add the remaining debug-related devices and component connections to the platform configuration.

  9. Add the devices and Component Connections for the devices listed in the table below.
    • Note: We have already added the devices or component connections highlighted below.

      M: = Master

      S: = Slave

      <number>: = Trigger or Slave value

      Device Type

      PCE device name

      AP index

      CoreSight Base Address

      Connected to

      DP

      ARMCS-DP_0

      NA

      NA

       


      AXI-AP

      CSMEMAP (0: AXI-AP) – APv1

      0

      NA

      ARMCS-DP_0

      APB-AP

      CSMEMAP (1: APB-AP) – APv1

      1

      NA

      ARMCS-DP_0

      Cortex-A72

      Cortex-A72_0

      1

      0x82010000

      S:1: CSCTI_0

      CTI

      CSCTI_0

      1

      0x82020000

       


      Cortex-A72

      Cortex-A72_1

      1

      0x82110000

      S:1: CSCTI_1

      CTI

      CSCTI_1

      1

      0x82120000

       


      Cortex-A53

      Cortex-A53_0

      1

      0x83010000

      S:1: CSCTI_2

      CTI

      CSCTI_2

      1

      0x83020000

       


      Cortex-A53

      Cortex-A53_1

      1

      0x83110000

      S:1: CSCTI_3

      CTI

      CSCTI_3

      1

      0x83120000

       


      Cortex-A53

      Cortex-A53_2

      1

      0x83210000

      S:1: CSCTI_4

      CTI

      CSCTI_4

      1

      0x83220000

       


      Cortex-A53

      Cortex-A53_3

      1

      0x83310000

      S:1: CSCTI_5

      CTI

      CSCTI_5

      1

      0x83320000

       


      AHB-AP-M

      CSMEMAP (2: AHB-AP-M) – APv1

      2

      NA

      ARMCS-DP_0

      Cortex-M3

      Cortex-M3

      2

      NA

      S:7: CSCTI_6

      CTI

      CSCTI_6

      2

      0xE0044000

      M: Cortex-M3

    • Click Save.

      PCE automatically builds the platform configuration.

    When complete, the Device Table is:

      Complete debug Devices tab

    The complete debug Component Connections is:

      Complete Component Connections tab

    Understanding the platform configuration debug activities

    If the build is successful, you can see which debug activities you can perform with the platform configuration.

    1. Click Debug Activities.

    There are two main types of debug activity:

    • Bare Metal Debug
      • For debugging bare-metal environments such as non-OS boot code, firmware, and test cases.
    • Linux Kernel and/or Device Driver Debug
      • For debugging the Linux kernel or Linux kernel device drivers and applications.

    The different activities let you connect to:

    • Individual cores (denoted by Cortex-X_<number>) when X is the core type and number is the core number.
      • Debugger starting and stopping only starts or stops the individual core, not the rest of the cores.
    • Symmetric Multiprocessing core sets (denoted by SMP or big.LITTLE).
      • Debugger starting and stopping starts and stops all the cores which are part of the SMP connection.For example, starting or stopping any core in a Cortex-A72 and Cortex-A53 big.LITTLE connection starts and stops the two Cortex-A72s and the 4 Cortex-A53s.

    Test the debug aspects of the platform configuration

    1. Test the platform configuration in the Development Studio perspective.

    To make sure the platform configuration is working as expected, test the following:

    • Whether you can connect to and debug (for instance, stop and start) all the individuals cores using Bare Metal Debug.
    • Whether you can connect to and debug (for instance, stop and start) all the SMP core sets using Bare Metal Debug.
    Previous Next