Arm Debugger Manual Configuration Tutorial

Tutorial on how to manually configure a platform configuration using Arm Development Studio's Platform Configuration Editor (PCE)


Overview Understanding CoreSight Understanding a target's debug and trace infrastructure Set up the platform configuration manually Manually configuring a platform configuration for debug Manually configuring a platform configuration for trace

Manually configuring a platform configuration for trace

In this section, we add the trace devices associated with the Cortex-A53 cluster, so that we can capture trace data for this cluster’s cores.

Below is a block diagram of the trace-related devices for the target’s Cortex-A53 cluster we are manually configuring:Diagram of the example target's trace infrastructure

Note:  The connections between the Cortex-A53 associated CTIs and the Cortex-A53 cluster CTM are not present to make the diagram clearer.

The trace data flow is:

  1. Each ETM generates trace data for its associated Cortex-A53 core.
  2. The generated trace data combines in one trace stream by two funnels, Funnel_0 and Funnel_1.
  3. The single trace stream is passed through an Embedded Trace FIFO (ETF).
  4. The ETF output is passed into another funnel, Funnel_2.
  5. The last funnel passes the single trace stream into a replicator to generate two identical trace streams.
  6. Each trace stream is passed to an TMC ETR to store the trace data into target memory and a TPIU to export the trace data off the target to a debug unit.

There is also a CTI, CTI_7, connected between the ETF, ETR, and TPIU and the CTM for the Cortex-A53 cluster which allows these trace components to stop the cores in the cluster under specific circumstances.

We now start adding the trace devices to the platform configuration.

Add trace devices and component connections to the platform configuration

In this section, we add the below to the platform configuration:

  1. A Trace Memory Controller (TMC) ETF.
  2. An ETM.
  3. A component connection between the Cortex-A53 and the ETM.
  4. A funnel.
  5. A component connection between the ETM and the funnel.
  6. The rest of the trace-related devices and component connections.

This exercise also covers good tests to check whether the platform configuration allows you to trace the target with the Arm Debugger.

  1. Add a TMC (ETF).

    Add a CSTMC to the CSMEMAP_1:

    Adding a CSTMC ETF

  2. Click on CSTMC.

    There are certain TMC settings which must be correct for Arm Debugger to use the TMC.

    • CORESIGHT_BASE_ADDRESS
      • The lower 32-bits of the CoreSight base address for the TMC.
    • CORESIGHT_BASE_ADDRESS_MSW
      • The higher 32-bits of the CoreSight base address for the TMC.
    • CONFIG_TYPE
      • The type the TMC is configured for.The choices are ETF, ETR, and Embedded Trace Buffer (ETB).
    • MEM_WIDTH
      • The width of the AMBA Trace Bus (ATB) into the ETF in bits.
    • *RAM_SIZE_BYTES
      • The size of the ETF RAM in bytes.

    Note: * means the device information entry appears after the CONFIG_TYPE is set.

    For our board, the details for the TMC are:

    • CORESIGHT_BASE_ADDRESS is 0x80010000.
    • CORESIGHT_BASE_ADDRESS_MSW is 0x0.
    • CONFIG_TYPE is ETF.
    • Leave RAM_SIZE_BYTES and MEM_WIDTH at the default values.
  3. Add an ETM to Cortex-A53_0.

    Add a CSETM for the Cortex-A53_0:

    Adding an ETM

  4. Click on CSETM.

    There are certain ETM settings which must be correct for Arm Debugger to use the ETM.

    • CORESIGHT_BASE_ADDRESS
      • The lower 32-bits of the CoreSight base address for the ETM.
    • CORESIGHT_BASE_ADDRESS_MSW
      • The higher 32-bits of the CoreSight base address for the ETM.
    • SUPPORTS_DATA_ADDRESS_TRACE
      • Whether the ETM supports data tracing.

     

    For our board, the details for the first Cortex-A53 ETM are:

    • CORESIGHT_BASE_ADDRESS is 0x83040000.
    • CORESIGHT_BASE_ADDRESS_MSW is 0x0.
    • SUPPORTS_DATA_ADDRESS_TRACE is False.
  5. Add a Component Connection between Cortex-A53_0 and CSETM.
  6. Add a CSTFunnel for the Cortex-A53 cluster and setup the CSTFunnel.

    For our board, the details for the Cortex_A53 cluster funnel are:

    • CORESIGHT_BASE_ADDRESS is 0x803C0000.
    • CORESIGHT_BASE_ADDRESS_MSW is 0x0.
  7. Add a Component Connection between the CSETM and the CSTFunnel on Slave Interface 0.

    You now have all the information you to add the remaining trace-related devices and component connections to the platform configuration.

  8. Add the devices and Component Connections for the devices listed in the table below.
  9. Note: We have already added the devices or component connections highlighted below.

    M: = Master

    S: = Slave

    <number>: = Trigger or Slave value

    Device Type

    PCE device name

    AP index

    CoreSight Base Address

    Connected to

    TMC (ETF)

    CSTMC_0

    1

    0x80010000

    S:0: CSTFunnel_2

    CTI

    CSCTI_7

    1

    0x80020000

    S:0: CSTMC_0

    S:1: CSTMC_1

    S:3: CSTPIU

    TPIU

    CSTPIU

    1

    0x80030000

     

    Funnel

    CSTFunnel_1

    1

    0x80040000

    S: CSTMC_0

    TMC (ETR)

    CSTMC_1

    1

    0x80070000

     

    Replicator

    CSATBReplicator

    1

    0x80120000

    S:0: CSTPIU

    S:1: CSTMC_1

    Funnel

    CSTFunnel_2

    1

    0x80150000

    S: CSATBReplicator

    ETM

    CSETM_0

    1

    0x83040000

    M: Cortex-A53_0

    S:0: CSTFunnel_0

    ETM

    CSETM_1

    1

    0x83140000

    M: Cortex-A53_1

    S:1: CSTFunnel_0

    ETM

    CSETM_2

    1

    0x83240000

    M: Cortex-A53_2

    S:2: CSTFunnel_0

    ETM

    CSETM_3

    1

    0x83340000

    M: Cortex-A53_3

    S:3: CSTFunnel_0

    Funnel

    CSTFunnel_0

    1

    0x830C0000

    S:0: CSTFunnel_1

  10. Click Save.

    PCE automatically builds the platform configuration.

When complete, Devices is:

 

Complete trace Devices tab

The complete trace Component Connections is:

Complete trace Component Connections tab

Test the trace aspects of the platform configuration

  1. Test the platform configuration in the Development Studio perspective.

To make sure the platform configuration is working as expected, test the following:

  • Make sure you can get trace data from each ETM using the ETR.
  • Make sure you can get trace data from each ETM using the TPIU.

Note on making changes to the platform configuration outside the PCE GUI

When configuring or modifying some target platform configurations, you might be required to make changes directly to the SDF or DTSL (.py) files without going through the PCE GUI.  If this is the case, you must rebuild the configDB and test the platform configuration before trying to connect to the target.

To rebuild the configDB, go to Window > Preferences > Arm DS > Configuration Database and click Rebuild database.

To test the platform configuration, in the Configuration Database dialog:

  1. Click Test platforms… .
  2. Select the platform configuration.
  3. Click OK.
  4. Resolve any errors found.
  5. Save the platform configuration.
  6. Rebuild the configDB.
  7. Repeat steps 1 – 7 until no errors remain.
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