Arm Debugger Manual Configuration Tutorial

Tutorial on how to manually configure a platform configuration using Arm Development Studio's Platform Configuration Editor (PCE)


Overview Understanding CoreSight Understanding a target's debug and trace infrastructure Set up the platform configuration manually Manually configuring a platform configuration for debug Manually configuring a platform configuration for trace

Understanding a target's debug and trace infrastructure

In the Understanding CoreSight section, you learned that CoreSight devices are used to enable debug and trace capability for a target.  In this section, we are going to look at what target information is required to create a platform configuration in Arm Development Studio.

In order to manually create a platform configuration for a target, you must know:

  • All the scan chain and CoreSight devices present.
  • The type and number of DPs.
  • The type, number, and index values of all APs.
  • How the different devices are connected together (known as the CoreSight topology).
  • Device-specific information such as implementation settings.

This information is usually found in tabular or block diagram form in the target’s documentation.

This tutorial focuses on an example target’s debug and trace infrastructure.  The target contains a two-core Cortex-A72 cluster, a four-core Cortex-A53 cluster, and a Cortex-M3.  The target is modeled on an Arm Development Platform and some CoreSight devices are left out intentionally for the purpose of this tutorial.  The target conforms to the Arm Debug Interface Architecture Specification ADIv5.0 to ADIv5.2 implemented by the Arm CoreSight SoC-400 Technical Reference Manual.  CoreSight SoC-400 uses AP version 1 (APv1).  

The table below lists the debug and trace infrastructure devices and component connections for the target described above:  

Note:

S: = Slave

<number>: = Trigger or Slave value

Device Type

PCE device name

AP index

CoreSight Base Address

Connected to

DP

ARMCS-DP_0

NA

NA

AXI-AP

CSMEMAP (0: AXI-AP) – APv1

0

NA

ARMCS-DP_0

APB-AP

CSMEMAP (1: APB-AP) – APv1

1

NA

ARMCS-DP_0

TMC (ETF)

CSTMC_0

1

0x80010000

S:0: CSTFunnel_2

CTI

CSCTI_7

1

0x80020000

S:0: CSTMC_0

S:1: CSTMC_1

S:3: CSTPIU

TPIU

CSTPIU

1

0x80030000

Funnel

CSTFunnel_1

1

0x80040000

S: CSTMC_0

TMC (ETR)

CSTMC_2

1

0x80070000

Replicator

CSATBReplicator

1

0x80120000

S:0: CSTPIU

S:1: CSTMC_1

Funnel

CSTFunnel_2

1

0x80150000

S: CSATBReplicator

Cortex-A72

Cortex-A72_0

1

0x82010000

S:1: CSCTI_0

CTI

CSCTI_0

1

0x82020000

Cortex-A72

Cortex-A72_1

1

0x82110000

S:1: CSCTI_1

CTI

CSCTI_1

1

0x82120000

Cortex-A53

Cortex-A53_0

1

0x83010000

S:1: CSCTI_2

S: CSETM_0

CTI

CSCTI_2

1

0x83020000

ETM

CSETM_0

1

0x83040000

S:0: CSTFunnel_0

Cortex-A53

Cortex-A53_1

1

0x83110000

S:1: CSCTI_3

S: CSETM_1

CTI

CSCTI_3

1

0x83120000

ETM

CSETM_1

1

0x83140000

S:1: CSTFunnel_0

Cortex-A53

Cortex-A53_2

1

0x83210000

S:1: CSCTI_4

S: CSETM_2

CTI

CSCTI_4

1

0x83220000

ETM

CSETM_2

1

0x83240000

S:2: CSTFunnel_0

Cortex-A53

Cortex-A53_3

1

0x83310000

S:1: CSCTI_5

S: CSETM_3

CTI

CSCTI_5

1

0x83320000

ETM

CSETM_3

1

0x83340000

S:3: CSTFunnel_0

Funnel

CSTFunnel_0

1

0x830C0000

S:0: CSTFunnel_1

AHB-AP-M

CSMEMAP (2: AHB-AP-M) – APv1

2

NA

ARMCS-DP_0

Cortex-M3

Cortex-M3

2

NA

S:7: CSCTI_6

CTI

CSCTI_6

2

0xE0044000

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