Arm Debugger Manual Configuration Tutorial

Understanding a target's debug and trace infrastructure

In the Understanding CoreSight section, you learned that CoreSight devices are used to enable debug and trace capability for a target.  In this section, we are going to look at what target information is required to create a platform configuration in Arm Development Studio.

In order to manually create a platform configuration for a target, you must know:

• All the scan chain and CoreSight devices present.
• The type and number of DPs.
• The type, number, and index values of all APs.
• How the different devices are connected together (known as the CoreSight topology).
• Device-specific information such as implementation settings.

This information is usually found in tabular or block diagram form in the target’s documentation.

This tutorial focuses on an example target’s debug and trace infrastructure.  The target contains a two-core Cortex-A72 cluster, a four-core Cortex-A53 cluster, and a Cortex-M3.  The target is modeled on an Arm Development Platform and some CoreSight devices are left out intentionally for the purpose of this tutorial.  The target conforms to the Arm Debug Interface Architecture Specification ADIv5.0 to ADIv5.2 implemented by the Arm CoreSight SoC-400 Technical Reference Manual.  CoreSight SoC-400 uses AP version 1 (APv1).  

The table below lists the debug and trace infrastructure devices and component connections for the target described above:  

Note:

S: = Slave

<number>: = Trigger or Slave value