CoreSight technology is the Arm solution for debug and trace in complex SoC designs. CoreSight consists of:
- A library of modular devices and component interconnects.
- Architected discovery and identification methods to allow for flexible system design.
- A standard for implementing the Arm Debug Interface for debug tools.
CoreSight provides the ability to read and modify register values of CPUs and peripherals and provides monitoring and triggering resources.
CoreSight trace allows for the continuous collection of system information for later analysis and includes:
- trace sources such as the Embedded Trace Macrocell (ETM).
- trace links such as the funnel and the replicator.
- trace sinks such as the Trace Memory Controller (TMC) Embedded Trace FIFO (ETF), the TMC Embedded Trace Router (ETR), and the Trace Port Interface Unit (TPIU).
Typically, CoreSight devices are behind a CoreSight Debug Access Port (DAP). A DAP presents a physical port to be connected to by external debug tools either using JTAG or Serial Wire Debug (SWD). A DAP is a DP connected to one or more Access Ports (APs or MEMAPs). The MEMAP types available are:
- Advanced Peripheral Bus Access Port (APB-AP).
- Advanced High Performance Bus Access Port (AHB-AP).
- Advanced eXtensible Interface Access Port (AXI-AP).
Below is a diagram of a DP.
All CoreSight systems include at least one ROM table. The ROM table allows an external debugger to discover the CoreSight devices on the target. Each entry in the ROM table contains an address offset that points to the base address of a device accessible through the MEMAP or another ROM table.
Below is a diagram of a ROM Table.
Arm systems have an Embedded Cross Trigger (ECT) that consists of Cross Trigger Interfaces (CTIs) and Cross Trigger Matrixes (CTMs).
CTIs send and receive trigger events through the Trigger Interface. Trigger events are mapped to channel events and transmitted through the Channel Interface. CTIs have programmable mappings between triggers and channels.
CTMs broadcast channel events through Channel Interfaces and enable the linking of CTIs.
Below is a diagram of an ECT.
Typically, the ECT is used for:
- Cross-halting CPUs.
- Simultaneous CPU restart.
- Trace collection trigger.
- Interrupt generation.
- Cross component mapping between CPU and FPGA subsystems.