What is a ROM Table?
Each ROM Table on the SoC contains a listing of the components that are connected to the DP or MEM-AP. These listings allow an external debugger or on-chip software to discover the CoreSight devices on the SoC. Systems with more than one debug component must include at least one ROM Table. ROM Tables are connected either to DPs or MEM-APs.
A ROM Table entry either contains an address offset for a component on the SoC, or a pointer to another ROM Table. You calculate the base address of the component by adding the component address offset to the ROM Table base address. If the ROM Table entry is a component address offset, the PRESENT bit of the ROM Table entry indicates whether the component is present in the system. The end of a ROM Table is marked by an all 0x0 entry or an entry at ROM Table offset 0xEFC.
In both ADIv5.x and ADIv6, ROM Tables can be nested, with no limit on the depth of the nesting. Nesting in this context means one ROM Table can point to another ROM Table.
The following diagram shows the placement and possible entries of a ROM Table that is connected to an APB-AP:
The location of the top-level ROM Table is determined by one of the following:
- The ROM Table base address register of the MEM-AP, BASE.
- On ADIv6 targets, by the ROM Table base address registers of the DP, BASEPTR0-BASEPTR1.
- An OS or debug monitor knowledge of the system memory map.