Understanding the CoreSight DAP

A tutorial describing the CoreSight Debug Access Port (DAP) and common Arm Development Studio DAP-related autodetection issues


Overview What is a Debug Access Port What is an Access Port What is a ROM Table Common DAP-related autodetection issues

What is an Access Port?

An Access Port (AP) is a port that is connected to a DP or debug link. An AP provides a bridge into another system on the SoC.

A Memory Access Port (MEM-AP) provides a window into a memory system. This window allows memory-mapped accesses to debug resources. Examples of debug resources are:

  • Debug registers of a core processor
  • Debug registers for trace components such as Embedded Trace Macrocell (ETM) and Trace Memory Controllers (TMC) instances, for example, Embedded Trace FIFO (ETF) and Embedded Trace Router (ETR)
  • Debug registers for CoreSight links such as Cross Triggering Interfaces (CTIs)
  • ROM Tables
  • Memory systems

ADIv5.x defines APv1. ADIv6 defines APv2. APv2 is not backwards-compatible with APv1.

Here are the AP types that are available:

  • Advanced Peripheral Bus Access Port (APB-AP)
    • For interfacing to APB memory systems
    • Typically, CoreSight component debug registers, like for Cortex-A and Cortex-R processors, are accessible through this AP.
  • Advanced High-performance Bus Access Port (AHB-AP)
    • For interfacing to AHB memory systems.
    • Typically, Cortex-M class debug and trace registers are accessible through this AP.
  • Advanced eXtensible Interface Access Port (AXI-AP)
    • For interfacing to AXI memory systems
  • JTAG Access Port (JTAG-AP)
    • For interfacing to legacy components such as pre-CoreSight processors. For example, Arm7, Arm9, and Arm11 processors.

The following diagram demonstrates the different AP types in a system with a JTAG/SWD debug link. An ADIv5-compliant system is used in the diagram:

Diagram of a DAP

In ADIv5, a DP supports up to 256 APs. In ADIv6, only the address space limits how many APs a DP can support.

The Identification Register (IDR) of the AP identifies the AP designer, variant, and type. If the IDR value is zero, this indicates that the AP is not present in the system. The IDR is defined in the ADI architecture specification.

In ADIv6, on-chip software is permitted to access the AP layer, which enables on-chip debug software to access multiple systems using the same APIs as external debuggers.

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