Debug and trace for Arm architecture up to Armv8. Whether it's legacy or the very latest, the DSTREAM probe family has it covered.
Parallel trace up to 19.2 Gbps, or serial trace (HSSTP, SETM) up to 60 Gbps
Capture extended trace even on the fastest targets to get a detailed picture of software execution.
Adapters for JTAG, CoreSight, TI and MIPI. Compatible with 3rd party IP and debuggers to give you maximum flexibility.
Second-generation debug and trace probe, enabling debug and widest bandwidth parallel trace up to 19.2Gbs over 32 pins, with an 8GB trace buffer and support for all Arm processors. Includes real-time dynamic monitoring to automatically adjust trace sampling between clock edges, and system autodetection with Arm Development Studio. Supports a range of target connectors including JTAG, MICTOR, CoreSight, and MIPI.
Full specifications Buy DSTREAM-PT
Second-generation Arm debug probe, enabling maximum debug visibility into Arm processors, with 2.4 Gbps parallel trace over 4 pins, streams trace data directly to host machine, system autodetection with Development Studio. Supports a range of target connectors including JTAG, MICTOR, and CoreSight.
Second-generation debug and high-speed serial trace probe with up to 60 Gbps combined lane rate, 8 GB trace buffer and system auto-detection with Arm Development Studio. It is optimized for the resolution of complex software, hardware and timing-related issues, and post-analysis of software execution without the need for any software or hardware instrumentation.
Full specifications Buy DSTREAM-HT
First-generation Arm debug probe enabling debug visibility into Arm processors, with 9.6 Gbps parallel trace or 20 Gbps serial trace, 4 GB trace buffer, system auto-detection with Development Studio. Supports a range of target connectors including JTAG, MICTOR, and CoreSight.
Arm Development Studio together with the DSTREAM debug probes includes powerful software utilities for SoC bring-up and interfaces for third-party IP support.
The CoreSight Access Tool (CSAT) provides a scriptable low-level interface to a target’s CoreSight Debug Access Port (DAP), which gives access to on-chip debug and system buses. CSAT is useful to perform initial bring-up tests before a debugger connection to the target is available.
CSAT enables the configuration of third-party IP connected to the DAP, for example custom instrumentation hardware, and can be used while a debugger is connected to an Arm processor. This enables the debug of complex hardware-related problems.
Arm target connection products implement powerful low-level target control via Python scripts. For example, this allows you to configure them to automatically refresh the watchdog timer while they are connected to the target, and work around hardware bugs.
Development Studio also uses Jython scripting for debug and trace configuration, making it simple to define complex trace topologies and helping you to route trace to Development Studio
RDDI is the main set of C APIs between Arm debuggers and DSTREAM devices. RDDI contains several API sets and these are supported by each device as follows:
Third-party debuggers or other customer-specific tooling for both Arm and other processor cores can connect to DSTREAM probes using the RDDI interface. Whilst RDDI is a C level API, other languages can be used, such as Java and Python. The firmware in DSTREAM family has a flexible architecture to connect to multiple Arm and third-party IP cores on an SoC via a single debug interface.
RDDI is freely available from within the Development Studio installation.
A low-level RDDI connection to DSTREAM units can be used to gain access to the JTAG scan-chains inside the target device. This enables the unit to be used for simple tasks such as production testing and flash programming.
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| DSTREAM | DSTREAM-ST | DSTREAM-PT | DSTREAM-HT | |
| Debug connectivity | JTAG and Serial-Wire Debug | |||
| Arm processor support | Any Arm processor based hardware target up to Armv8 with CoreSight trace supported | |||
| On target trace | Yes | Yes | Yes | Yes |
| External parallel trace | 9.6 Gb/s (up to 16 pins) | 2.4 Gb/s (up to 4 pins) | 19.2 Gb/s (up to 32 pins) | 2.4 Gb/s (up to 4 pins) |
| External serial trace | Up to 20 Gb/s Arm HSSTP or Marvell® SETM. Requires high-speed serial trace probe (HSSTP), available separately. |
- | - | Up to 60 Gb/s Arm HSSTP or Marvell® SETM protocol |
| Specifications | ||||
| Maximum number of supported cores | 128 | 1022 | 1022 | 1022 |
| Cores + CoreSight devices limit | Support for up to 254 CoreSight devices (including up to 128 CPUs) | Support for up to 1022 CoreSight devices (including CPUs) | Support for up to 1022 CoreSight devices (including CPUs) | Support for up to 1022 CoreSight devices (including CPUs) |
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| JTAG frequency | 60 MHz | 180 MHz | 180 MHz | 180 MHz |
| Memory download | Up to 2.5 MB/s | Up to 12 MB/s | Up to 12 MB/s | Up to 12 MB/s |
| Trace buffer | 4 GB | None - streamed to host PC | On probe 8 GB trace memory store | On probe 8 GB trace memory store |
| Host connectivity | USB 2.0, Ethernet | USB 3.0, Gigabit Ethernet | USB 3.0, Gigabit Ethernet | USB 3.0, Gigabit Ethernet |
| 3rd party support | Flexible architecture to support 3rd party IP and debuggers Device bring-up and test utilities Remote target reset |
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| Trace capture | 16-bit wide trace capture at 300 MHz DDR (600 Mbit/s per pin) | 4-bit wide trace capture at up to 300 MHz DDR (600 Mbit/s per pin) | 32-bit wide trace capture at up to 300 MHz DDR (600 Mbit/s per pin) | Up to 6 lanes Up to 12.5 Gb/s per lane 60 Gb/s max. total bandwidth |
| Interface Vref | 1.2V - 3.3V (configurable by target) | |||
| Minimum software requirements | Arm Development Studio or DS-5 | Arm Development Studio or DS-5 5.27 | Arm Development Studio 2019.0 | Arm Development Studio 2019.0-1 |
| Learn more | Learn more | Learn more | Learn more | |