High-speed serial trace and debug probe

Debug probe with high-speed serial trace up to 60 Gbps combined lane rate, with an 8GB trace buffer to capture detailed trace information from CoreSight and custom IP devices. It enables the resolution of complex software, hardware and timing-related issues, and post-analysis of software execution without the need for any software or hardware instrumentation.

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Features

  • Debug and trace on Arm processors with CoreSight trace
  • USB 3.0 and Gigabit Ethernet for direct or remote host connections
  • 8GB trace buffer for extended trace periods
  • Customizable to support ASIC
  • Code download speeds of up to 12 MB per second
  • Support for up to 1022 CoreSight devices
  • Flexible trace clock positioning relative to trace data
  • Remote target reset
  • Device bring-up and test utilities
  • Flexible architecture to support 3rd party IP and debuggers

Specifications

Debug protocol Arm HSSTP, Marvell SETM
Single-lane rate bandwidth Up to 12.5 Gbps single-lane line rate
High-speed serial trace bandwidth Up to 60 Gbps
Number of lanes 1 to 6
JTAG/SWD signal voltage 1.2V to 3.3V configurable by target
Maximum JTAG clock speed 180 MHz
Supported macrocells CoreSight Trace for example ETM, ETB, STM, ITM
Target connectors 40-way SAMTEC ERF8 (Debug and Trace)
Arm 20-pin 0.1" pitch header (Alt. Debug when JTAG signals need to be sent separately)
Software requirements Arm Development Studio
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What's included?

Main unit, High-speed Serial Trace (HSSTP) probe and connecting ribbon cable
Unified 5V power supply unit (PSU) and associated cables

Target connectors:

  • USB 3.0 and GbE cables
  • 40-way HSSTP ribbon cable
  • JTAG 20 and CoreSight™ 10/20 ribbon cables
  • Adapters for TI-14 and MICTOR 38 connectors

Documentation

Document Number Document Title Description
101760 DSTREAM-HT Getting Started Guide Describes the DSTREAM-HT debug and trace system which allows you to debug and optimize your software on Arm processor-based hardware targets.
101761 DSTREAM-HT System and Interface Design Reference Guide Describes the interfaces of the DSTREAM-HT debug and trace system, with details about designing Arm architecture-based ASICs and PCBs.