Arm Socrates

Arm Socrates is a tool that guides a user through the selection, configuration and creation of Arm IP, to achieve integration ready IP in hours instead of days.

  • Contains a catalog of Arm IP to aid in IP discovery and selection, along with identification of exactly what you need to download from Arm to use the IP.
  • Intelligently configure and build Arm IP.
  • Get the system performance you expect, through Arm IP that is configured, built, and integrated right first time.
  • Simplify configuration of Arm CoreLink IP. Arm Socrates automatically creates a CoreLink interconnect that is right first time.
Socrates top level picture

Intelligent interconnect construction and configuration of Arm IP

Socrates tool value picture

Arm Socrates IP Tooling helps system designers to select and intelligently configure Arm IP, reducing the time to achieve integration ready IP to hours instead of days.

Socrates IP Tooling enables hardware, software, and verification teams to get the system performance they expect - through Arm IP that is configured, built, and integrated right first time. It is the only fully integrated solution for use with Arm System IP.

Socrates IP Tooling  simplifies the configuration of Arm CoreLink System IP. Automatically create a CoreLink interconnect that is right first time.

Internal benchmarking has shown an 8x improvement in schedule when design teams use Socrates IP Tooling for the first time!

CoreLink interconnect creation

Modern system interconnects are highly configurable IP blocks that need to connect across multiple power and voltage domains to maximize SoC connectivity. Some of the problems facing interconnect design teams today include:

  • SoCs are getting larger, with more components and greater connectivity. 
  • SoCs are composed of modular subsystems that bring reuse and timing closure issues. 
  • Interconnect backplane must offer multiple services:
    • Lowest latency from CPU to memory. 
    • QoS guarantees. 
    • Coherency. 
    • Virtualization.
    • Clock and power management.

Socrates addresses all of these issues and guides architects and designers through the configuration and creation of an optimized and viable CoreLink Interconnect. Socrates generates the interconnect µarchitecture, stitches it together, and validates the top level interconnect. Architects and designers can start with the high-level specification, generate the µArchitecture, and create the deliverables (RTL, design specification, testbench, and testcases). Architects and designers can visualize each stage of the design as well as validate the viability and quality using design rule checks.

CoreLink creation vastly reduces the time needed to implement and validate a complex on-chip AMBA® interconnect – down from several months to weeks.

Socrates catalog screen shot

Arm IP selection configuration and build in minutes

Socrates includes the Arm IP catalog, which helps users select Arm IP and guides them through a construction, configuration and build in minutes.

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

Not answered SMMUv2 - Arm Corelink-MMU500 on Xilinx Zynq Ultrascale+
  • CoreLink MMU-500 System Memory Management Unit
  • Armv8-A
  • SMMUv2
0 votes 35 views 0 replies Started yesterday by Ciro Donnarumma Answer this
Suggested answer boundary concept
  • AMBA
  • AXI
  • AHB
0 votes 331 views 3 replies Latest 3 days ago by harrykayn Answer this
Suggested answer State Machine for AHB-Lite Protocol
  • ahb-lite
  • AHB
0 votes 198 views 3 replies Latest 5 days ago by Colin Campbell Answer this
Suggested answer Amba Adaptive Traffic Profiles question
  • AMBA
0 votes 130 views 1 replies Latest 8 days ago by Matteo Maria Andreozzi Answer this
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
  • AXI
0 votes 209 views 2 replies Latest 9 days ago by Zax Answer this
Suggested answer Assertion for Multiple Transfer on APB Bus
  • APB
  • AMBA
  • Bus Architecture
0 votes 143 views 2 replies Latest 9 days ago by Rakesh Venkatesan Answer this
Not answered SMMUv2 - Arm Corelink-MMU500 on Xilinx Zynq Ultrascale+ Started yesterday by Ciro Donnarumma 0 replies 35 views
Suggested answer boundary concept Latest 3 days ago by harrykayn 3 replies 331 views
Suggested answer State Machine for AHB-Lite Protocol Latest 5 days ago by Colin Campbell 3 replies 198 views
Suggested answer Amba Adaptive Traffic Profiles question Latest 8 days ago by Matteo Maria Andreozzi 1 replies 130 views
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? Latest 9 days ago by Zax 2 replies 209 views
Suggested answer Assertion for Multiple Transfer on APB Bus Latest 9 days ago by Rakesh Venkatesan 2 replies 143 views