Arm Socrates significantly reduces the time to select, configure and create Arm IP that is error free and ready for SoC integration.
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Intelligent interconnect construction and configuration of Arm IP
CoreLink interconnect creation
Modern system interconnects are highly configurable IP blocks that need to connect across multiple power and voltage domains to maximize SoC connectivity. Some of the problems facing interconnect design teams today include:
- SoCs are getting larger, with more components and greater connectivity.
- SoCs are composed of modular subsystems that bring reuse and timing closure issues.
- Interconnect backplane must offer multiple services:
- Lowest latency from CPU to memory
- QoS guarantees
- Clock and power management
Socrates addresses all of these issues and guides architects and designers through the configuration and creation of an optimized and viable CoreLink Interconnect. Socrates generates the interconnect µarchitecture, stitches it together, and validates the top level interconnect. Architects and designers can start with the high-level specification, generate the µArchitecture, and create the deliverables (RTL, design specification, testbench, and testcases). Architects and designers can visualize each stage of the design as well as validate the viability and quality using design rule checks.
CoreLink creation vastly reduces the time needed to implement and validate a complex on-chip AMBA® interconnect – down from several months to weeks.
Arm Socrates IP Tooling helps system designers to select and intelligently configure Arm IP, reducing the time to achieve integration ready IP to hours instead of days.
Socrates IP Tooling enables hardware, software, and verification teams to get the system performance they expect - through Arm IP that is configured, built, and integrated right first time. It is the only fully integrated solution for use with Arm System IP.
Socrates IP Tooling simplifies the configuration of Arm CoreLink System IP. Automatically create a CoreLink interconnect that is right first time.
Internal benchmarking has shown an 8x improvement in schedule when design teams use Socrates IP Tooling for the first time!
Arm IP selection configuration and build in minutes
Socrates includes the Arm IP catalog, which helps users select Arm IP and guides them through a construction, configuration and build in minutes.
Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.Arm training courses Open a support case
|Not answered||CHI protocol cache line states||0 votes||58 views||0 replies||Started 11 hours ago by S_Seth||Answer this|
|Not answered||STM32F769i-Discovery IP Camera Interface||0 votes||80 views||0 replies||Started yesterday by Kiran bhat||Answer this|
|Suggested answer||Store operations where the cache line is already cached (ACE protocol)||2 votes||6200 views||9 replies||Latest yesterday by het||Answer this|
|Not answered||Best most recent text on ARM arch||0 votes||127 views||0 replies||Started 4 days ago by d.ry||Answer this|
|Not answered||Readunique and cleanunique transactions in ACE protocol||0 votes||166 views||0 replies||Started 4 days ago by het||Answer this|
|Suggested answer||Raspberry pi 3 and .net 5 coreclr||1 votes||2076 views||2 replies||Latest 4 days ago by delinaty||Answer this|
|Not answered||CHI protocol cache line states Started 11 hours ago by S_Seth||0 replies 58 views|
|Not answered||STM32F769i-Discovery IP Camera Interface Started yesterday by Kiran bhat||0 replies 80 views|
|Suggested answer||Store operations where the cache line is already cached (ACE protocol) Latest yesterday by het||9 replies 6200 views|
|Not answered||Best most recent text on ARM arch Started 4 days ago by d.ry||0 replies 127 views|
|Not answered||Readunique and cleanunique transactions in ACE protocol Started 4 days ago by het||0 replies 166 views|
|Suggested answer||Raspberry pi 3 and .net 5 coreclr Latest 4 days ago by delinaty||2 replies 2076 views|