CoreSight Creator Characteristics
CoreSight Creator is a tool that guides a user through the configuration and creation of a CoreSight Debug and Trace subsystem with minimal design engineering action. It takes licensed CoreSight Debug and Trace system IP, which is a library of configurable IP components used by designers to create a CoreSight Debug and Trace subsystem to ease hardware and software debug.
CoreSight Creator requires the TM100 CoreSight SoC-400 library. All of the individual CoreSight SoC-400 components are supported as well as the CoreSight Embedded Logic Analyzer, ELA-500, and System Trace Macrocontroller, STM and STM-500.
The figure below shows the functionality that is available with a CoreSight Creator license.
CoreSight Creator can be used to simplify the configuration and creation of a CSSYS component and make it ready for integration into a larger system design. You can iterate over the configuration flow to refine your CSSYS design and perform checks that ensure validity and correctness at every stage.
The figure below shows the workflow to create and refine a CSSYS.
Important Interfaces for CoreSight IP and CoreSight Creator
Link Components for CoreSight IP and CoreSight Creator
Link Components in CoreSight Creator
Trace Sinks for CoreSight IP and CoreSight Creator
Trace Sinks in CoreSight Creator
Time Stamp for CoreSight IP and CoreSight Creator
- Many trace sources support Time Stamp. Time Stamp is added to the trace packets at periodic intervals.
- Time Stamp allows temporal correlation of trace from different sources. It also allows approximate time-based profiling of various trace sources.
- All trace sources should use a common Time Stamp Generator.
Time Stamp Components in CoreSight Creator
Cross Trigger Distribution for CoreSight IP and CoreSight Creator
Event Components in CoreSight Creator
DAP & Access Block Diagram
DAP & Access Blocks in CoreSight Creator
Trace Memory Controller (TMC) for CoreSight IP and CoreSight Creator
TMC replaces the CoreSight Embedded Trace Buffer (ETB) and requires an additional IP license. It allows trace capture using:
- 2-pin serial-wire debug interface
- System memory
- Existing high-speed links on the SoC
TMC can also be alternatively configured as a trace FIFO. This configuration:
- Averages trace port bandwidth
- Reduces trace overflows
- Reduces trace port width and clocking
System Trace Macrocell (STM) for CoreSight IP and CoreSight Creator
STM supports high-bandwith trace instrumentation and requires an additional IP license. CPU (or other device) writes cause STM to generate trace packets. STM enables:
- Software instrumentation
- Hardware Event Observation
- High-level software view for debug
- System performance monitoring and tuning
- Internal SoC signal visibility