Overview

Arm CoreSight Creator is a tool that guides the user through the configuration and creation of a CoreSight Debug and Trace subsystem with minimal design engineering action. It takes licensed CoreSight Debug and Trace system IP, which is a library of configurable IP components used by designers to create a CoreSight Debug and Trace subsystem to ease hardware and software debug. 


  • A guide on software optimization.
  • IP-XACT Whitepaper

    A study by IP Tooling architect David Murray on how IP-XACT metadata can be used in various design flows to ease IP integration

    Access Whitepaper
  • On The Road to Building a System in a Day

    This webinar shows how Arm Socrates IP Tooling can help system designers dramatically reduce the time it takes to configure and integrate their SoCs

    View Webinar
A cog on a square representing developers.

Automated

Automatic micro-architecture synthesis of a CoreSight Ddebug and Trace subsystem

Searching for support within arm.

Validated

Multiple Design Rule Checks ensure the system is viable and valid, making it correct-by-construction

A processor chip.

Generated

Deliverables such as RTL, testbenches, and test cases are generated at the click of a button

Highlights

CoreSight Creator reads the IP-XACT description of each CoreSight component and identifies the typical interfaces needed to describe and specify a CoreSight subsystem. It uses in-built intelligence to automatically synthesize a micro-architecture for the subsystem. This in-built intelligence removes the need for extensive knowledge of the CoreSight architecture. CoreSight Creator offers guided configuration and intelligent integration of a CoreSight Debug and Trace subsystem efficiently and quickly.

Key Features

CoreSight Creator reads the IP-XACT description of each CoreSight component and identifies the typical interfaces needed to describe and specify a CoreSight subsystem. It uses in-built intelligence to automatically synthesize a micro-architecture for the subsystem. A rules-based methodology removes the need for extensive knowledge of the CoreSight architecture. CoreSight Creator offers guided configuration and intelligent integration of a CoreSight Debug & Trace subsystem quickly.

CoreSight Creator Features

  • Programmatic data-driven IP integration
  • Full IEEE1685-2009 (IP-XACT) compliance
  • Real-time verification with DRCs
  • Auto-generated RTL & testbench outputs
  • Auto-creation of optimised System IP
  • Fast & easy design restructuring
  • Rich graphical user interface (GUI)

CoreSight Creator Characteristics

CoreSight Creator is a tool that guides a user through the configuration and creation of a CoreSight Debug and Trace subsystem with minimal design engineering action. It takes licensed CoreSight Debug and Trace system IP, which is a library of configurable IP components used by designers to create a CoreSight Debug and Trace subsystem to ease hardware and software debug. 

CoreSight Creator requires the TM100 CoreSight SoC-400 library.  All of the individual CoreSight SoC-400 components are supported as well as the CoreSight Embedded Logic Analyzer, ELA-500, and System Trace Macrocontroller, STM and STM-500. 

The figure below shows the functionality that is available with a CoreSight Creator license.


CoreSight Creator can be used to simplify the configuration and creation of a CSSYS component and make it ready for integration into a larger system design. You can iterate over the configuration flow to refine your CSSYS design and perform checks that ensure validity and correctness at every stage.

The figure below shows the workflow to create and refine a CSSYS.


    Important Interfaces for CoreSight IP and CoreSight Creator


    Link Components for CoreSight IP and CoreSight Creator


    Link Components in CoreSight Creator




    Trace Sinks for CoreSight IP and CoreSight Creator



    Trace Sinks in CoreSight Creator



    Time Stamp for CoreSight IP and CoreSight Creator


    • Many trace sources support Time Stamp. Time Stamp is added to the trace packets at periodic intervals.
    • Time Stamp allows temporal correlation of trace from different sources. It also allows approximate time-based profiling of various trace sources.
    • All trace sources should use a common Time Stamp Generator.

    Time Stamp Components in CoreSight Creator




    Cross Trigger Distribution for CoreSight IP and CoreSight Creator




    Event Components in CoreSight Creator




    DAP & Access Block Diagram




    DAP & Access Blocks in CoreSight Creator




    Trace Memory Controller (TMC) for CoreSight IP and CoreSight Creator

    TMC replaces the CoreSight Embedded Trace Buffer (ETB) and requires an additional IP license. It allows trace capture using:

    • 2-pin serial-wire debug interface
    • System memory
    • Existing high-speed links on the SoC

    TMC can also be alternatively configured as a trace FIFO. This configuration:

    • Averages trace port bandwidth
    • Reduces trace overflows
    • Reduces trace port width and clocking

    System Trace Macrocell (STM) for CoreSight IP and CoreSight Creator


    STM supports high-bandwith trace instrumentation and requires an additional IP license. CPU (or other device) writes cause STM to generate trace packets. STM enables:

    • Software instrumentation
    • Hardware Event Observation

    STM provides:

    • High-level software view for debug
    • System performance monitoring and tuning
    • Internal SoC signal visibility



      Resources

      Useful Information

      Whitepaper: Lessons from the field - IP/SoC integration techniques that work

      Whitepaper - IP-XACT Standardized IP Interfaces for Rapid IP Integration

      White Paper - Solving Next Generation IP Configurability

       

      IP-XACT (IEEE1685 standard)

      IP-XACT describes the metadata of IP designs and flows and the interconnection of IP interfaces in a standard specification. The IP-XACT extension mechanism supports user-defined vendor features to implement specific tool or flow features, for example to store vendor-specific IP metadata like GUI-related data. These new extensions published by Accellera enable cross-company IP-XACT usage in emerging areas of design such as analog-mixed signal, physical design planning, and power.

      More information regarding IP-XACT can be found at:  http://accellera.org/downloads/standards/ip-xact.

       

      Interesting blogs

       

      New Arm IP Tooling Suite Reduces Significantly SoC Integration Time

      Even More Integration and Automation for Arm-based Designs

      System Assembly Through Intelligent Configuration

       

      Related Products

      Arm IP tooling is designed and optimized to be used with Arm IP, system IP, and tools.

      Cortex Processors

      CoreSight Debug & Trace

      CoreLink Interconnect

      Mali GPU

      Memory Controllers

      System Controllers