Explore the Scalable Vector Extension (SVE)

Scalable Vector Extension (SVE) is a vector extension for AArch64 execution mode for the A64 instruction set of the Armv8-A architecture. Unlike other SIMD architectures, SVE does not define the size of the vector registers, but constrains it to a range of possible values, from a minimum of 128 bits up to a maximum of 2048 in 128-bit wide units. Therefore, any CPU vendor can implement the extension by choosing the vector register size that better suits the workloads the CPU is targeting. The design of SVE guarantees that the same program can run on different implementations of the instruction set architecture without the need to recompile the code.

Many instructions of the extension use predicate registers to mask the lanes for operating on partial vectors. The SVE instruction set also provides gather loads and scatter stores, truncating stores, and signed/unsigned extended loads.

The SVE2 (Scalable Vector Extension version two) is a superset of SVE and Neon, and allows for more function domains in data-level parallelism. SVE2 inherits the concept, vector registers, and operation principles of SVE.

For information about porting your codes to an SVE-enabled system, see the Porting to Arm SVE resources section.

Arm Compiler for Linux

Commercial C/C++/Fortran compiler and math libraries from Arm for Linux user-space server and HPC applications with complete SVE and SVE2 support.

Compile for SVE

Arm Instruction Emulator

Analyze your SVE or SVE2 code by emulating SVE (or SVE2) instructions binaries using Arm Instruction Emulator.

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Learning resources

Introducing SVE

Scalable Vector Extension (SVE) is the next-generation SIMD instruction set for Armv8-A (AArch64). This topic introduces the new architectural features it brings.

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A sneak peek into SVE and VLA

An overview of SVE with information on the new registers, the new instructions, and the Vector Length Agnostic (VLA) programming technique, with some examples.

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Application to Machine Learning

In this white paper, code examples are presented that show how to vectorize some of the core computational kernels that are part of machine learning system.

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Papers filed, in a formal order.

SVE programmers guide

Learn more about the Scalable Vector Extension with our series of guides. From the fundamentals to more advanced concepts, these guides provide an introduction to the SVE and SVE2 extensions to the Arm Armv8-A architecture.

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Porting to Arm SVE resources

To learn about porting your applications to Arm, watch the Porting to Arm SVE webinar. Using the Arm Compiler for Linux, this webinar focuses on helping you generate code for SVE-enabled, Armv8-A based systems.

 To learn more about SVE, Vector Length Agnostic (VLA) programming, and the methodology of porting your code, read the Porting and Optimizing HPC Applications for Arm SVE guide. The guide:

  • Introduces the Arm Scalable Vector Extension (SVE)
  • Introduces Vector Length Agnostic (VLA) programming, with examples
  • Recommends steps and tools to use to port your application
  • Advises on thread mapping
  • Introduces how to emulate SVE instructions with Arm Instruction Emulator (ArmIE)


Information regarding SVE tools

Q: How do I get access to SVE tools?
Download Arm Compiler for Linux and Arm Instruction Emulator to compile and run SVE code on non-SVE platforms.

Q: Where can I get support when emulating SVE instructions with Arm Instruction Emulator?
Contact Arm Support and we will get in touch.